Senior Verification Architect & Tech Lead

Cadence Design Systems, Inc.; Austin (TX); On-site; USD 140,000 - 200,000; Full time

Job summary

Cadence Design Systems, Inc. is seeking a Senior DV Engineer in Austin, TX to lead verification strategy and architecture for complex ASIC/SoC designs.

You will design scalable testbenches, BFMs, and coverage-driven plans while guiding junior engineers and collaborating with design, architecture, and emulation teams. You will drive constrained‑random testing, formal verification, and GLS oversight to ensure high functional coverage and timely sign‑off on verification milestones.

Qualifications

• 4–7 years of hands‑on DV experience in semiconductor/ASIC/SoC.
• Bachelor or Master in Electronics or related field.
• Experience with testbench architecture, constrained‑random testing, and formal verification is a plus.

Responsibilities

• Define verification strategy and architecture for the project.
• Design scalable, reusable testbenches with BFMs, monitors, scoreboards, and checkers.
• Lead debugging and root‑cause analysis with design engineers.
• Implement constrained‑random stimulus and formal verification techniques.
• Monitor and analyze functional and code coverage metrics.
• Oversee gate‑level simulations to validate timing and reset behavior.

Skills

UVM.SystemVerilog

Verilog

Testbench development

Education

B.E./B.Tech or M.Tech in Electronics or related field

Tools

UVM/SystemVerilog

Verilog

Job description

Cadence Design Systems, Inc. is seeking a Senior DV Engineer in Austin, TX to lead verification strategy and architecture for complex ASIC/SoC designs.

You will design scalable testbenches, BFMs, and coverage-driven plans while guiding junior engineers and collaborating with design, architecture, and emulation teams. You will drive constrained‑random testing, formal verification, and GLS oversight to ensure high functional coverage and timely sign‑off on verification milestones.