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Normal Computing, based in Mountain View, is seeking a Design Verification Engineer to verify AI-enabled ASICs and raise the bar for verification flows. You will work on thermodynamic ASIC verification, testbench environments, and coverage to tapeout, applying advanced DV techniques.
The ideal candidate has 5+ years in digital verification at a semiconductor or EDA company, deep SystemVerilog/UVM expertise, and hands-on experience with vManager, Xcelium, and Jasper, plus Python or Perl
Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.
As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and help set the bar for the AI-assisted verification flows we are building for ourselves. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.
Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout.
AI-Assisted Verification: Review AI-generated verification collateral and help define what good looks like, so the tools the team builds raise the bar rather than lower it.
Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally.
5+ years of experience in digital verification at a major semiconductor or EDA tool company
Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
Excellent written and spoken communication skills: you can hold the room in a design review as credibly as you hold a debug session
Hands-on use of LLMs or agentic tools in verification workflows
Exposure to analog, mixed-signal, or unconventional compute verification
Equal Employment Opportunity Statement
Normal Computing is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or any other legally protected status.
Accessibility Accommodations
Normal Computing is committed to providing reasonable accommodations to individuals with disabilities. If you need assistance or an accommodation due to a disability, please let us know at accommodations@normalcomputing.com.
Privacy Notice
By submitting your application, you agree that Normal Computing may collect, use, and store your personal information for employment-related purposes in accordance with our Applicant Privacy Notice.