AI-Driven ASIC Design & Verification Engineer

Analog Devices; Durham (NC); On-site; USD 116,960 - 160,820; Full time

Benefits offered by this job

Medical insurance

Vision insurance

Dental coverage

401(k) matching

Paid time off

Job summary

Analog Devices, Inc. is seeking an ASIC Design and Verification Engineer focused on AI-enabled tool integration. You will develop agentic AI solutions to accelerate IC design and verification across multiple engineering domains, bridging digital and analog workflows.

You will collaborate with SVV teams, build automation, and apply AI/ML techniques to improve productivity while maintaining robust design verification practices. A strong background in System Verilog/UVM is essential.

Qualifications

• 5+ years of experience in IC design and verification.
• Experience with LLM-related techniques: prompt engineering, RAG, vector databases.
• Strong scripting skills in Python and Bash.
• Proficiency with System Verilog/UVM and C-based test bench development.

Responsibilities

• Evaluate and integrate Agentic AI tools with IC design/verification workflows.
• Develop libraries of custom instructions, skills, and automation scripts for AI tools.
• Apply ML/agentic AI techniques to enhance EDA tools.
• Connect APIs/SDKs to design databases.
• Educate users and deliver training on AI tools.
• Collaborate with design/verification engineers to improve productivity.

Skills

IC design

System Verilog/UVM

Python

Bash

Git

Linux

Debugging

Documentation

Communication

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

GitHub Actions

Jenkins

Job description

Analog Devices, Inc. is seeking an ASIC Design and Verification Engineer focused on AI-enabled tool integration. You will develop agentic AI solutions to accelerate IC design and verification across multiple engineering domains, bridging digital and analog workflows.

You will collaborate with SVV teams, build automation, and apply AI/ML techniques to improve productivity while maintaining robust design verification practices. A strong background in System Verilog/UVM is essential.