Senior DRAM Architecture Lead: Memory Controller & ECC

PhantaField; Santa Clara (CA); On-site; USD 200,000 - 260,000; Full time

Job summary

PhantaField is seeking a senior engineer to own Side S64 logic, refresh, ECC, and PHY for its first 3D DRAM die. You will define channels, drive design choices, and lead verification efforts, reporting to the CEO.

You will oversee the first-silicon PHY selection, JEDEC HBM5 efforts, and stability of the stack while coordinating with the DRAM circuit lead and verification teams. This is a high-impact, on-site role at PhantaField’s Santa Clara facility.

Qualifications

• 10+ years of DRAM architecture or HBM controller design.
• Writing SystemVerilog RTL.
• RAS and ECC design: SECDED, scrub and repair.
• Directing verification and DFT contractors or partner teams.
• Memory-controller or PHY integration on a tape-out.

Responsibilities

• Define the channels, pseudo-channels and density map.
• Design refresh so it hides inside the JESD270-4 timing windows and never stalls the host.
• Write the RTL for ECC, the repair controller and regulator control. Direct the verification and DFT contractors.
• Choose the first-silicon PHY: listed 28 nm PHY IP or a custom design. Own the bought SI/PI and IR-drop analysis through the stack.
• Track the JEDEC HBM5 work and keep the JESD270-4 fallback alive.

Skills

SystemVerilog RTL

DRAM architecture

HBM controller design

ECC design

Verification leadership

Job description

PhantaField is seeking a senior engineer to own Side S64 logic, refresh, ECC, and PHY for its first 3D DRAM die. You will define channels, drive design choices, and lead verification efforts, reporting to the CEO.

You will oversee the first-silicon PHY selection, JEDEC HBM5 efforts, and stability of the stack while coordinating with the DRAM circuit lead and verification teams. This is a high-impact, on-site role at PhantaField’s Santa Clara facility.