Senior SRAM Architect — 3D SRAM & Packaging

EDA CAREERS, (Technology Futures Inc).; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Performance bonus

Equity

Job summary

EDA CAREERS, (Technology Futures Inc.) seeks a Senior SRAM Memory Circuit Design Engineer (Architect) to lead 3D SRAM development in Silicon Valley, with remote possibilities for highly skilled designers.

You will define memory array architectures, design peripheral circuits, and own tests and validation from concept through tapeout, collaborating with architecture, device, and packaging teams.

Qualifications

• Experience in SRAM memory circuit design and array architectures.
• Define memory array architecture, organization, and read/write/standby schemes for thyristor-based cells.
• Design peripheral circuits including sense amplifiers, write drivers, wordline/bitline drivers, decoders, timing control, and power management.
• Design for test (DFT/BIST), redundancy and repair, and ECC strategies; support RTL for silicon bring-up.

Responsibilities

• Architect memory circuits for 3D SRAM from array to product macros.
• Lead design and verification across process, voltage, and temperature corners.

Skills

Simulation

Layout review

Test Chips

Memory design

DFT/BIST

ECC strategies

3D SRAM

Job description

EDA CAREERS, (Technology Futures Inc.) seeks a Senior SRAM Memory Circuit Design Engineer (Architect) to lead 3D SRAM development in Silicon Valley, with remote possibilities for highly skilled designers.

You will define memory array architectures, design peripheral circuits, and own tests and validation from concept through tapeout, collaborating with architecture, device, and packaging teams.