Senior Director, Chip Tech & Product Lead

Astera Labs; San Jose (CA); On-site; USD 260,000 - 295,000; Full time

Job summary

Astera Labs in San Jose, CA seeks a Product Technical Chip Lead (Senior Director/AVP) to drive end-to-end success of UALink switching products. You will connect architecture, design, validation, firmware, systems, and operations to ensure alignment and on-time execution across the full lifecycle.

You will lead cross-functional teams, own chip tapeout, and shape engineering culture while delivering scalable, high-performance silicon for rack-scale AI and hyperscale data centers.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 15+ years of experience across architecture, silicon design, validation, systems.
• Proven track record of developing large-scale chips (300mm²+) through successful tapeout.

Responsibilities

• Own the full technical lifecycle of the product line from architecture to customer enablement.
• Drive chip development from RTL to GDSII, including tapeout milestones.
• Lead development of large-scale chips (300-400mm²) using 2.5D/3D packaging and chiplets.
• Translate requirements into clear priorities and execution paths.
• Own chip tapeout and sign-off with emphasis on chip quality.
• Lead cross-functional teams across engineering functions.
• Establish scalable processes and data-driven decision making.

Skills

Executive leadership

Cross-functional collaboration

RTL design

Design verification

DFT / manufacturing test strategies

Strong communication

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's degree (preferred)

Tools

2.5D/3D packaging

chiplet-based architectures

PCIe

Ethernet

UALink/UCIe knowledge

Job description

Astera Labs in San Jose, CA seeks a Product Technical Chip Lead (Senior Director/AVP) to drive end-to-end success of UALink switching products. You will connect architecture, design, validation, firmware, systems, and operations to ensure alignment and on-time execution across the full lifecycle.

You will lead cross-functional teams, own chip tapeout, and shape engineering culture while delivering scalable, high-performance silicon for rack-scale AI and hyperscale data centers.