VP, Physical Design & Chiplet Architecture

Astera Labs; San Jose (CA); On-site; USD 251,000 - 375,000; Full time

Job summary

Astera Labs seeks a VP of Physical Design to lead full-chip physical design for next-generation switching products with UCIe and UALink. You will drive multi-die architectures, tapeouts, and performance targets in collaboration with architecture, digital design, packaging, and silicon teams.

You will mentor a growing PD team, ensure robust timing closure, power and area optimization, and lead efforts across 7nm or below node implementations.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience in physical design and implementation of complex SoCs or ASICs.
• Proven track record leading physical design teams and delivering multiple successful tapeouts in advanced process nodes (7nm or below).
• Deep expertise in chiplet architectures, interposer design, and die-to-die interface implementation.
• Strong understanding of advanced packaging technologies including 2.5D and 3D integration.
• Expert-level knowledge of physical design flows, timing closure, power optimization, and signoff methodologies.
• Experience managing and scaling engineering teams of 20+ people.

Responsibilities

• Lead end-to-end physical design execution for complex multi-die switching products with UCIe and UALink connectivity
• Drive chip-level floorplanning, power planning, placement, routing, and timing closure for advanced node designs
• Establish physical design methodologies and best practices for interposer-based chiplet architectures and die-to-die interfaces
• Own physical design quality metrics including timing, power, area, and manufacturability across multiple concurrent projects

Skills

Physical design leadership

Team leadership

Timing closure

Interposer design

Chiplet architectures

High-speed SerDes

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree or PhD in Electrical Engineering or related field

Tools

Cadence

Synopsys

Job description

Astera Labs seeks a VP of Physical Design to lead full-chip physical design for next-generation switching products with UCIe and UALink. You will drive multi-die architectures, tapeouts, and performance targets in collaboration with architecture, digital design, packaging, and silicon teams.

You will mentor a growing PD team, ensure robust timing closure, power and area optimization, and lead efforts across 7nm or below node implementations.