Senior Digital VLSI Design Engineer

Broadcom Inc.; Fort Collins (CO); On-site; USD 121,900 - 195,000; Full time

Benefits offered by this job

Annual bonus

Equity grant

Medical insurance

Dental and vision insurance

401(k) matching

ESPP (Employee Stock Purchase Program)

Employee assistance program

Paid holidays

Paid time off

Paid family leave

Job summary

Broadcom Inc. is seeking a Senior Digital VLSI Design Engineer in Fort Collins, CO. The role demands deep expertise in synthesis, DFT, CDC/RDC sign-off and control of high-speed interfaces to deliver robust IPs to SOC teams.

You will own synchronization strategies across multi-clock domains, review architecture with chip leads, and guide testability and DFT decisions early in the cycle while mentoring the broader design team to improve sign-off quality.

Qualifications

• BSEE required, MSEE/PHD preferred.
• 8+ years of related experience.
• Experience with structural and functional verification of crossings.

Responsibilities

• Define and enforce synchronization strategies across multi-clock domains.
• Own the constraint creation process for synthesis and full-chip CDC/RDC methodology.
• Review testability and DFT design, clocking and reset architectures early in the design cycle.
• Mentor design team on Synthesis, DFT, CDC/RDC best practices.
• Drive automated flows to streamline sign-off for multi-site global teams.

Skills

Synthesis

DFT

CDC/RDC sign-off

Metastability awareness

Education

BSEE

MS/PhD preferred

Tools

SpyGlass CDC/RDC

SpyGlass Lint

JasperGold

Meridian

Job description

Job Description

We are seeking a Senior Digital VLSI Design Engineer with deep expertise in Synthesis, DFT, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign‑off for high speed complex IPs to be delivered to the SOC teams. In this role, you will be the technical authority responsible for defining and enforcing synchronization strategies across complex, multi‑clock domains in advanced process nodes. You will own the constraint creation process for synthesis, full‑chip CDC/RDC methodology, establishing rigorous constraints and waivers to ensure zero‑defect silicon. You will collaborate closely with Architecture and Chip Lead teams to review the testability and DFT design, clocking and reset architectures early in the design cycle, identifying potential metastability or reset‑glitch issues before RTL freeze. The ideal candidate has 8+ years of experience and a mastery of structural and functional verification of crossings using industry‑standard tools (e.g., SpyGlass CDC/RDC, Spyglass Lint, JasperGold, or Meridian). Experience with high‑speed interfaces such as SerDes, LPDDR5/6, DDR4/5 or HBM, where asynchronous boundaries are critical, is highly desired. As a Senior Engineer, you are expected to mentor the broader design team on Synthesis, DFT, CDC/RDC best practices and drive automated flows to streamline sign‑off for multi‑site global teams.

Requirements

BSEE required, MSEE/PHD preferred. 8+ years of related experience.

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 to USD 195,000.00. As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans; 401(k) participation including company matching; Employee Stock Purchase Program (ESPP); Employee Assistance Program (EAP); company paid holidays; paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Equal Opportunity Employer

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.