Senior Signal Integrity Engineer

Broadcom Inc.; Wayne (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants and annual equity awards

Comprehensive benefits package

Job summary

Broadcom Inc. is seeking a Senior SI/PI Engineer to own signal and power integrity analysis for high-speed boards, packages and architectures. Collaborate with hardware, ASIC, SERDES, packaging and layout teams from early design through lab bring-up.

You will build 2.5D/3D EM models, perform time- and frequency-domain simulations, and validate designs in the lab using VNAs, TDRs, and high-bandwidth scopes.

Qualifications

• 12+ years of practical experience in high-speed digital design, SI, and PI.
• Solid understanding of transmission line theory, S-parameters, crosstalk, jitter, EMI/EMC, and PDN concepts.

Responsibilities

• Build 2.5D/3D EM models for high-speed channels and PCB stackups.
• Perform time- and frequency-domain simulations for SerDes and high-speed interfaces.
• Assist in AC/DC PDN simulations to evaluate impedance and transient noise.
• Provide layout constraints, stackup recommendations, and routing rules.
• Validate simulations with VNAs, TDRs, and high-bandwidth scopes.
• Debug SI/PI issues during board bring-up and root-cause degradations.
• Automate simulation flows and data processing with Python/TCL.

Skills

High-speed SI/PI

SerDes experience

RF/EMI fundamentals

Education

Electrical Engineering degree (BS/MS/PhD)

Tools

Ansys HFSS

Cadence Sigrity

HSPICE

Keysight ADS

Job description

About the Role

We are looking for a Senior SI/PI Engineer to join our hardware engineering team. In this role, you’ll own the signal and power integrity analysis for our high-speed boards, packages, and system architectures. You will work directly with hardware, ASIC, SERDES, packaging, and layout engineers from early architecture trade-offs all the way through lab bring-up and characterization. If you enjoy building accurate 3D simulation models, developing optimized solutions, and validating designs in lab, this role is for you.

What You’ll Do

Modeling & Simulation

Build 2.5D/3D EM models for high-speed channels, package substrates, connectors, and PCB stackups. Perform time- and frequency-domain simulations for high-speed serial links (SerDes) and parallel interfaces (DDR/HBM).

PDN Analysis

Assist in AC/DC power delivery network simulations to evaluate impedance targets, transient noise, and IR drop across boards and packages.

Design Optimization

Provide clear layout constraints, stackup recommendations, and routing rules to hardware and layout teams. Optimize custom package designs, connector breakouts, and practical via designs. Iterate as bottlenecks are discovered.

Lab Characterization

Validate simulations in the lab using VNAs, TDRs, BERTs, and real-time oscilloscopes. Correlate measurement data back to your models to refine future design rules.

Debug & Bring-up

Partner with hardware teams during board bring-up to debug SI/PI issues and root-cause signal degradation or power noise.

Automation

Leverage scripts (Python, TCL) to automate simulation flows, data processing, and design checks.

What We’re Looking For

Degree

BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.

Experience

12+ years of practical experience in high-speed digital design, signal integrity, and power integrity.

Fundamentals

Solid understanding of transmission line theory, S-parameters, crosstalk, jitter, EMI/EMC, and PDN concepts.

Simulation Tools

Hands‑on proficiency with tools like Ansys HFSS/SiWave, Cadence Sigrity/Allegro, Keysight ADS, or HSPICE.

Interfaces

Direct experience simulating and analyzing high-speed interfaces (e.g., PCIe, 56G/112G/224G SerDes, DDR4/5, or HBM).

Lab Skills

Comfortable operating high-frequency test equipment (VNAs, TDRs, high‑bandwidth scopes), probing techniques, and performing model‑to‑hardware correlation.

Nice to Have

Familiarity with high-speed PCB laminates, stackups, via designs, and manufacturing trade‑offs. Experience writing Python or TCL scripts to automate EDA tools.

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package

Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.