Senior Digital Verification Engineer - ASIC/FPGA Lead

SpaceX; Sunnyvale (CA); On-site; USD 210,000 - 355,000; Full time

Benefits offered by this job

Stock options

Long-term incentives

Medical, vision, dental

401(k)

Disability insurance

Life insurance

Paid parental leave

Paid vacation

Job summary

SpaceX is seeking a Principal Design Verification Engineer (Silicon Engineering) to lead digital ASIC/FPGA verification across blocks and systems. You will drive verification plans, manage milestones, and contribute to pre-silicon and post-silicon activities while collaborating with cross-disciplinary teams in a fast-paced space environment.

The role demands a hands-on, self-starting engineer with strong coding and problem-solving skills, capable of handling constrained random verification, RTL

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.

Responsibilities

• Responsible for digital ASIC and/or FPGA verification at block and system level.
• Lead and execute verification test plan, development, and milestones from beginning to end.
• Contribute towards pre-silicon verification, chip bring-up and post-silicon validation.
• Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs.

Skills

Design verification

Test bench development

OO programming

Python scripting

Constrained random verification

UVM/OVM/VMM

RTL design

Chip bring-up

Post-silicon validation

Education

Bachelor's degree in EE/CE/CS

Advanced degree in EE/CE

Job description

SpaceX is seeking a Principal Design Verification Engineer (Silicon Engineering) to lead digital ASIC/FPGA verification across blocks and systems. You will drive verification plans, manage milestones, and contribute to pre-silicon and post-silicon activities while collaborating with cross-disciplinary teams in a fast-paced space environment.

The role demands a hands-on, self-starting engineer with strong coding and problem-solving skills, capable of handling constrained random verification, RTL