Lead ASIC Verification Engineer - Digital & FPGA

SpaceX; Palo Alto (CA); On-site; USD 210,000 - 355,000; Full time

Benefits offered by this job

Medical, vision, and dental coverage

401(k) retirement plan

Employee Stock Purchase Plan

Stock options

Job summary

SpaceX in Palo Alto is seeking a Principal Design Verification Engineer (Silicon Engineering) to lead digital ASIC/FPGA verification for space and ground infrastructure. You will design test benches, verification plans, and drive milestones.

The role requires 10+ years in design verification, a bachelor’s in engineering, and expertise in UVM/OVM/VMM, Python scripting, and RTL bring-up. Willingness to work extended hours; competitive compensation.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or computer science.
• 10+ years of design verification and test bench development experience.
• Experience with UVM/OVM/VMM verification methodologies.
• Experience with RTL design, chip bring-up, and post-silicon validation.

Responsibilities

• Lead digital ASIC and/or FPGA verification at block and system level.
• Design and execute verification test plans, develop test benches, and meet milestones.
• Contribute to pre-silicon verification, chip bring-up, and post-silicon validation.
• Act as a self-starter and collaborate with cross-disciplinary teams.

Skills

UVM/OVM/VMM

Test benches

Constrained-random verification

Object-oriented programming

Test plan development

Coverage modeling

RTL design

Chip bring-up

Education

Bachelor's degree in electrical engineering, computer engineering, or computer science

Advanced degree in electrical engineering or computer engineering

Tools

Python

Job description

SpaceX in Palo Alto is seeking a Principal Design Verification Engineer (Silicon Engineering) to lead digital ASIC/FPGA verification for space and ground infrastructure. You will design test benches, verification plans, and drive milestones.

The role requires 10+ years in design verification, a bachelor’s in engineering, and expertise in UVM/OVM/VMM, Python scripting, and RTL bring-up. Willingness to work extended hours; competitive compensation.