Digital IC Design Verification Engineer

Snapchat, Inc.; Washington (District of Columbia); On-site; USD 164,000 - 259,000; Full time

Benefits offered by this job

RSU equity

Paid parental leave

Comprehensive medical coverage

Job summary

Snap Inc seeks a Custom IC Layout Engineer to join the MicroDisplay Electronics at SPECS. You will design analog and mixed-signal ICs for AR, collaborating with digital and analog teams, and craft layouts to meet area, performance, and power goals.

Proficiency in Cadence Virtuoso and Mentor Calibre is required, with 5+ years of relevant experience. You will contribute to parasitic extraction, tape-out readiness, and design reviews in a fast-paced environment.

Qualifications

• BSEE or equivalent; 5+ years in custom IC layout.
• Experience with SRAM, IPs like PLLs, Bandgaps, ADCs/DACs.
• Proficient in Cadence Virtuoso and Calibre for layout and verification.

Responsibilities

• Perform cell and block layout for analog/mixed-signal circuits.
• Support IC floor planning and place & route of full-chip designs.
• Create design documentation and perform parasitic extraction.

Skills

Analog/mixed-signal design

Layout verification

Team collaboration

Scripting (TCL, Python)

Education

BSEE or equivalent

Tools

Cadence Virtuoso

Mentor Calibre

Linux scripting

Job description

Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves, live in the moment, learn about the world, and have fun together.The Company operates Snapchat , a visual messaging app that enhances your relationships with friends, family, and the world, and Specs Inc. , a wholly-owned subsidiary dedicated to making computing more human, in addition to Bitmoji , Saturn, and other digital services.Specs Inc. is a wholly-owned subsidiary of Snap Inc. dedicated to making computing more human. The company develops Specs, advanced eyewear that seamlessly integrates digital experiences into the physical world.Specs feature see-through lenses that place digital objects directly into three-dimensional space, powered by Snap OS, a proprietary, context-aware operating system designed for natural interaction with your hands and voice.Specs Inc. also provides Lens Studio, a full suite of advanced developer tools that powers immersive augmented reality experiences across Specs, Snapchat, and other services.We’re looking for a Custom IC Layout Engineer to join the MicroDisplay Electronics at SPECSWhat you’ll do:Work as part of a multi-disciplinary team designing display ICs for ARWork closely with digital and analog logic, circuit and physical design engineers & other custom layout engineersPerform cell and block layout of Analog and Mixed-Signal circuit functions, meeting design rules and performanceCraft reusable scripts and methodologies that help automate design flow, repeatability and efficiencyImplement circuit layout strategies for optimal area, performance and power goals.Support IC floor planning and place & route of full chip digital designs with digital and analog IPProvides schedule, and cost inputs to program managementCreate and present design documentation for internal design reviewsExecute parasitic extraction of circuit layout and iterate design improvementsKnowledge, Skills & Abilities:Strong working knowledge of custom (transistor-level) layout, including matching techniquesStrong working knowledge of Cadence Virtuoso (Layout and Schematic) tool suiteStrong working knowledge of Mentor/Siemens Calibre tool suite (DRC, LVS, Extraction)Scripting and automation, such as TCL, SKILL, Perl, Python and Shell scripts in Linux environmentExperience and capability to execute project tape out verification including DRC, ERC and LVSExtensive understanding of signal integrity, reliability, layout effects (EM, IR drop) and other considerationsKnowledge of tool flows and techniques for achieving foundry DFM requirementsTrack record of prior detailed design and custom layout experience of various types of designs such as SRAM, level shifters, IO design (ESD, latch-up), PLLs, Bandgaps, ADCs, DACs and amplifiers.Minimum Qualifications:BSEE or relevant years of experience5+ years in directly applicable work performing custom layoutOptional – see preferred QualificationsPreferred Qualifications:Detailed understanding of 22nm and below CMOS foundry design node rules and requirements.Experience with both Analog and Memory layoutsExcellent technical, documentation and verbal skills working with engineering and management teamsKnowledge of ASIC IC test and characterizationUnderstanding of digital design and place and route principles\"Default Together\" Policy at Snap: At Snap Inc. we believe that being together in person helps us build our culture faster, reinforce our values, and serve our community, customers and partners better through dynamic collaboration. To reflect this, we practice a “default together” approach and expect our team members to work in an office 4+ days per week.At Snap, we believe that having a team of diverse backgrounds and voices working together will enable us to create innovative products that improve the way people live and communicate. Snap is proud to be an equal opportunity employer, and committed to providing employment opportunities regardless of race, religious creed, color, national origin, ancestry, physical disability, mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, pregnancy, childbirth and breastfeeding, age, sexual orientation, military or veteran status, or any other protected classification, in accordance with applicable federal, state, and local laws. EOE, including disability/vets.We are an Equal Opportunity Employer and will consider qualified applicants with criminal histories in a manner consistent with applicable law (by example, the requirements of the San Francisco Fair Chance Ordinance and the Los Angeles Fair Chance Initiative for Hiring, where applicable).Our Benefits : Snap Inc. is its own community, so we’ve got your back! We do our best to make sure you and your loved ones have everything you need to be happy and healthy, on your own terms. Our benefits are built around your needs and include paid parental leave, comprehensive medical coverage, emotional and mental health support programs, and compensation packages that let you share in Snap’s long-term success!CompensationIn the United States, work locations are assigned a pay zone which determines the salary range for the position. The successful candidate’s starting pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions. The starting pay may be negotiable within the salary range for the position. These pay zones may be modified in the future.Zone A (CA, WA, NYC) :The base salary range for this position is $173,000-$259,000 annually.Zone B :The base salary range for this position is $164,000-$246,000 annually.Zone C :The base salary range for this position is $147,000-$220,000 annually.This position is eligible for equity in the form of RSUs.If you believe this job description is missing required pay transparency information, please submit a report through this form : Job Description Pay Range Disclosure .