Senior Digital Layout Engineer – Custom ASICs & Macros

Apple Inc.; San Diego (CA); Hybride; USD 167 000 - 296 000; Plein temps

Avantages offerts par ce poste

Medical coverage

Dental coverage

Retirement benefits

Stock programs

Relocation assistance

Résumé du poste

Apple Inc. in San Diego is seeking a lead Digital Layout Designer to join the silicon design effort.

You will design complex custom layouts for digital circuits in deep SubMicron CMOS technologies, review floorplans with circuit designers, and run layout verification tools to ensure PDV clean layouts. You will collaborate with the circuit design team to plan work, negotiate tradeoffs, and interpret LVS/DRC/ERC reports to meet engineering specs.

Qualifications

• Bachelor's degree and 10+ years of relevant experience.
• Experience in custom layout design of deep SubMicron CMOS circuits.
• Proficient in layout floorplanning and hierarchical layout assembly.
• Ability to interpret RC, LVS, DRC, ERC reports and optimize layouts.

Responsabilités

• Deliver PDV clean layout for digital circuits in deep SubMicron CMOS technologies.
• Review floorplans and complex circuits with designers.
• Run layout verification tools on megacells and ensure specifications are met.
• Collaborate with circuit design team to plan work and negotiate tradeoffs.
• Interpret LVS, DRC, and ERC reports to optimize layouts and fix issues.

Connaissances

Custom layout

Submicron CMOS

Floorplanning

RC delay

Electromigration

Mentor Graphics

Cadence

Scripting

Layout automation

Memory layout

Communication

Team collaboration

Formation

Bachelor's degree

Outils

Mentor Graphics

Cadence

Description du poste

Apple Inc. in San Diego is seeking a lead Digital Layout Designer to join the silicon design effort.

You will design complex custom layouts for digital circuits in deep SubMicron CMOS technologies, review floorplans with circuit designers, and run layout verification tools to ensure PDV clean layouts. You will collaborate with the circuit design team to plan work, negotiate tradeoffs, and interpret LVS/DRC/ERC reports to meet engineering specs.