Senior Remote Digital IC Design & Verification Engineer

SNAP, Inc.; Washington; Hybrid; USD 164,000 - 259,000; Full time

Benefits offered by this job

Equity in RSUs

Job summary

Snap Inc. seeks a Custom IC Layout Engineer to join the SPECS team working on AR display ICs. You will perform transistor-level layout, collaborate with analog/digital designers, and optimize area, performance and power while building automated flows.

You will contribute to parasitic extraction, DFM compliance, and tape-out verification in a fast-paced environment that values innovation and cross-functional teamwork.

Qualifications

• BSEE or equivalent with 5+ years in custom layout.
• Strong knowledge of transistor-level layout and matching techniques.
• Experience with 22nm or below CMOS nodes is preferred.

Responsibilities

• Design and lay out analog and mixed-signal circuit functions for AR displays.
• Collaborate with digital/analog teams and other layout engineers.
• Automate design flow with scripts to improve efficiency and repeatability.
• Support floor planning and place & route of full-chip designs with IP.
• Prepare design docs for internal reviews and perform parasitic extraction.

Skills

Custom layout

Cadence Virtuoso

Mentor Calibre

Scripting TCL

Python

Circuit layout

Tape-out verification

DFM awareness

Education

BSEE

Tools

Cadence Virtuoso

Mentor Calibre

Job description

Snap Inc. seeks a Custom IC Layout Engineer to join the SPECS team working on AR display ICs. You will perform transistor-level layout, collaborate with analog/digital designers, and optimize area, performance and power while building automated flows.

You will contribute to parasitic extraction, DFM compliance, and tape-out verification in a fast-paced environment that values innovation and cross-functional teamwork.