Senior Digital IC Design Engineer – RTL/Tapeout

Sandia National Laboratories; Albuquerque (NM); On-site; USD 118,000 - 236,000; Full time

Benefits offered by this job

Flexible work options

Relocation assistance

Generous vacation

Medical benefits

Job summary

Sandia National Laboratories in Albuquerque seeks a highly skilled Digital IC Design Engineer to deliver advanced ASIC solutions for mission and laboratory customers. You will translate system needs into robust RTL through tapeout, coordinating with analog/MEMS/photonics and physical-design teams.

On a typical day you review schedules, write block-level specs, develop RTL, extend verification environments, and support tapeout with timing and power analyses.

Qualifications

• A Bachelor's degree in a relevant discipline plus a minimum of five years of directly related experience, or an equivalent combination of directly relevant education and engineering or scientific experience that demonstrates the knowledge, skills, and ability to perform independent research and development.
• Ability to obtain and maintain a DOE Q clearance.

Responsibilities

• Review project schedules and milestones (tapeout targets, design reviews, lab deliverables) with the PI/tech lead, identify blockers (PDK/tool updates, interface questions, verification gaps), and drive closure
• Convert customer/mission needs into clear block-level specifications (performance, power, area, radiation tolerance, interfaces, testability) and maintain requirements-to-design traceability
• Develop and maintain RTL (control, datapath/DSP, interfaces), integrate IP, and implement clean CDC/reset strategies and appropriate low-power/clocking techniques.
• Build and extend verification environments; run regressions; analyze failures; close coverage; and perform lint, CDC, and formal checks with documented evidence for reviews
• Run or coordinate synthesis and implementation handoff; review timing/power reports; debug critical paths; and iterate with physical design to meet constraints
• Collaborate closely with analog/MEMS/photonics teams on mixed-signal interfaces (ADC/DAC timing, bias/control, sensor protocols) and validate behavior against system-level models

Skills

RTL design

Verilog/SystemVerilog

UVM

Digital design

Timing closure

Education

Bachelor's degree in a relevant discipline

Tools

EDA toolflows

Job description

Sandia National Laboratories in Albuquerque seeks a highly skilled Digital IC Design Engineer to deliver advanced ASIC solutions for mission and laboratory customers. You will translate system needs into robust RTL through tapeout, coordinating with analog/MEMS/photonics and physical-design teams.

On a typical day you review schedules, write block-level specs, develop RTL, extend verification environments, and support tapeout with timing and power analyses.