RTL & PD Design Engineer for AI ASICs

Normal Computing; New York (NY); On-site; USD 130,000 - 180,000; Full time

Job summary

Normal Computing is seeking an RTL and PD Design Engineer to take and optimize RTL through synthesis and the backend to produce GDSII ready for tapeout. You will own RTL from microarchitecture to tapeout, writing SystemVerilog, and collaborating with verification engineers to test with both conventional and formal methods.

This role bridges architecture, verification, RTL design, and physical design, requiring close partnership with fab reps and architecture teams to drive design decisions and

Qualifications

• Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route.

Responsibilities

• RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.

Skills

SystemVerilog RTL

Synthesis & P&R

Tapeouts

Debugging

Tools

EDA tooling

GDSII flow

Job description

Normal Computing is seeking an RTL and PD Design Engineer to take and optimize RTL through synthesis and the backend to produce GDSII ready for tapeout. You will own RTL from microarchitecture to tapeout, writing SystemVerilog, and collaborating with verification engineers to test with both conventional and formal methods.

This role bridges architecture, verification, RTL design, and physical design, requiring close partnership with fab reps and architecture teams to drive design decisions and