RTL/PD Design Engineer for Tapeout-Ready ASICs

Normal Computing Corporation; New York (NY); On-site; USD 120,000 - 170,000; Full time

Job summary

Normal Computing seeks an RTL and PD Design Engineer to own RTL from microarchitecture to tapeout, delivering GDSII-ready designs. You will write SystemVerilog, collaborate with architecture, verification, and fab teams, and guide designs through synthesis, place-and-route, CTS, timing, LVS/DRC, and tapeout.

Strong candidates have multiple tapeouts, hands-on production RTL in SystemVerilog, and the ability to shape architecture when specifications are still evolving.

Qualifications

• Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route.
• At least three tapeouts in your background, from any node and any company size.
• Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront.
• Strong debugging instincts across simulation, waveforms, and formal counterexamples.
• Ability to work directly with architects, design verification, and fab representatives.

Responsibilities

• Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces.
• Work with architecture to translate high-level specifications into implementable microarchitectures.
• Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage.
• Take synthesized RTL gates through the full backend design flow, including floorplanning, detailed place and route, CTS, DFT insertion, timing closure, LVS/DRC.
• Participate in design reviews and contribute to architecture decisions, not just implementation.
• Create and signoff tapeout checklists, and support post-silicon characterization bring-up as needed.

Skills

SystemVerilog

RTL Design

Debugging

Collaboration

Tapeouts

Synthesis

Place-and-Route

Education

Bachelor's degree in Electrical Engineering

Tools

EDA tooling

Job description

Normal Computing seeks an RTL and PD Design Engineer to own RTL from microarchitecture to tapeout, delivering GDSII-ready designs. You will write SystemVerilog, collaborate with architecture, verification, and fab teams, and guide designs through synthesis, place-and-route, CTS, timing, LVS/DRC, and tapeout.

Strong candidates have multiple tapeouts, hands-on production RTL in SystemVerilog, and the ability to shape architecture when specifications are still evolving.