Senior Digital Design Engineer - Memory RTL

Micron Technology, Inc.; Boise (ID); Hybride; USD 120 000 - 180 000; Plein temps

Résumé du poste

Micron Technology, Inc. seeks a Senior Digital Design Engineer to develop DRAM digital and mixed‑signal blocks.

You will handle RTL design, implementation, synthesis, timing analysis, and power optimization across the RTL-to-GDS flow, collaborating with architecture, verification, and physical design teams to meet product specifications and PPA goals. The role focuses on high‑performance, energy‑efficient designs, with emphasis on front-end quality checks, timing closure, and reusable

Qualifications

• Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years of experience in digital ASIC/RTL design.
• Proven experience developing RTL for complex digital designs from specification through implementation handoff.
• Strong knowledge of ASIC front-end design flows including RTL design, functional verification, logic synthesis, CDC/RDC analysis, and static timing analysis (STA).
• Experience developing and maintaining design constraints (SDC), including clocks, timing exceptions, I/O constraints, and multi-model multi-corner timing scenarios.
• Proficiency with Verilog/SystemVerilog and industry-standard simulation tools.
• Experience with low-power design methodologies, UPF-based power intent, timing constraints, and PPA optimization.

Responsabilités

• Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets.
• Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities.
• Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality.
• Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios.
• Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market.

Connaissances

RTL design

Verilog/SystemVerilog

Static timing analysis (STA)

Logic synthesis

CDC/RDC analysis

Power optimization

UPF-based power intent

Design constraints (SDC)

Timing closure

Cross-functional collaboration

Formation

Master’s degree in Electrical Engineering

Bachelor’s degree in Electrical Engineering

Outils

Industry-standard simulation tools

Description du poste

Micron Technology, Inc. seeks a Senior Digital Design Engineer to develop DRAM digital and mixed‑signal blocks.

You will handle RTL design, implementation, synthesis, timing analysis, and power optimization across the RTL-to-GDS flow, collaborating with architecture, verification, and physical design teams to meet product specifications and PPA goals. The role focuses on high‑performance, energy‑efficient designs, with emphasis on front-end quality checks, timing closure, and reusable