Senior Digital IP & RTL Design Engineer

Micron Technology; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology in Idaho is seeking an experienced digital design engineer to shape architecture, design, and verification of competitive IP for DRAM. The role partners with layout, modeling, and CAD teams to deliver high-quality memory solutions.

You will translate complex specs into robust verification requirements, mentor teams, and leverage AI tools to boost design efficiency. A strong background in high-speed digital design and RTL is preferred.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field, or equivalent experience.
• 6+ years of experience in digital or semiconductor design.
• Ability to translate specifications into clear design and verification requirements.
• Strong written and verbal communication skills.
• Effective time management and prioritization skills.

Responsibilities

• Develop competitive digital IPs for advanced DRAM products.
• Define design and verification requirements from specifications and reference designs.
• Build high-level behavioral and algorithmic models for architecture verification.
• Design IP using RTL or custom methodologies and guide layout and verification teams.
• Collaborate with standards, CAD, modeling, and verification teams to improve design quality.
• Leveraging AI tools to develop, improve design quality and efficiency.

Skills

High-speed design

STA compliance

RTL design

Architectural models

Behavioral models

Memory technologies

Education

Bachelor's degree in Electrical Engineering

Job description

Micron Technology in Idaho is seeking an experienced digital design engineer to shape architecture, design, and verification of competitive IP for DRAM. The role partners with layout, modeling, and CAD teams to deliver high-quality memory solutions.

You will translate complex specs into robust verification requirements, mentor teams, and leverage AI tools to boost design efficiency. A strong background in high-speed digital design and RTL is preferred.