Senior Digital Design Engineer - Front-End ASIC & Equity

Credo; San Jose (CA); On-site; USD 140,000 - 170,000; Full time

Benefits offered by this job

Discretionary bonus

Equity

Full range of medical benefits

Job summary

A technology company in San Jose seeks a Senior Digital Design Engineer to lead ASIC design efforts. Candidates should have 5–10 years of experience and a solid foundation in digital design, including proficiency in Verilog/SystemVerilog. The role involves creating microarchitecture specs, collaborating with teams for successful tape-outs, and ensuring product quality through rigorous testing. The position offers a competitive salary and a range of benefits, including bonuses and equity.

Qualifications

• 5–10 years of experience in digital ASIC design.
• Strong understanding of digital logic design.
• Hands-on experience with gate-level simulations and chip bring-up.

Responsibilities

• Write microarchitecture and/or design specifications.
• Architect/design, implement, and debug complex logic blocks.
• Collaborate with cross-functional teams to ensure product quality.

Skills

Digital ASIC design

Verilog/SystemVerilog RTL design

Testing and validation

Scripting languages (Python, Tcl, Perl, Shell)

Effective communication

Education

BS or MS in Electrical Engineering, Computer Engineering, or related field

Job description

A technology company in San Jose seeks a Senior Digital Design Engineer to lead ASIC design efforts. Candidates should have 5–10 years of experience and a solid foundation in digital design, including proficiency in Verilog/SystemVerilog. The role involves creating microarchitecture specs, collaborating with teams for successful tape-outs, and ensuring product quality through rigorous testing. The position offers a competitive salary and a range of benefits, including bonuses and equity.