Senior Digital Design Architect & Chip Lead

Micron Technology, Inc; Boise, Northern (ID, KY); Hybrid; USD 178,000 - 389,000; Full time

Job summary

Micron Technology, Inc. is seeking a Principal Digital Design Engineer / Chip Lead to own chip architecture, lead RTL development, and drive timing closure for high-speed interfaces. You will manage tape-out processes with a small, senior team and collaborate with DV, analog, and PD peers to deliver a tape-ready design.

The role requires extensive SystemVerilog experience, strong synthesis/STA skills, and leadership capability. AI-assisted productivity is explicitly valued.

Qualifications

• BS/MS/PhD in Electrical or Computer Engineering or related field.
• 10+ years of ASIC/digital design experience with at least one tape-out.
• Expert-level SystemVerilog RTL design and coding best practices.
• Strong experience with logic synthesis tools and SDC timing constraints.
• Proficiency with RTL simulation and debugging tools.
• Solid understanding of CDC analysis methodologies and tools.
• Demonstrated IP integration experience in mixed IP environments.
• Ability to lead a small technical team and own outcomes.
• Strong written communication and documentation skills.
• Comfort leveraging AI to boost productivity.

Responsibilities

• Define top-level chip architecture and integrate hard macros with soft IP.
• Author, review, and maintain synthesizable RTL for control blocks and top-level integration.
• Develop and own chip-level timing constraints and clock-domain strategy.
• Drive logic synthesis and optimization for PPA targets across blocks.
• Coordinate DV staff for assertion-based, coverage-driven, and formal verification.
• Define interfaces between PHY hard macro, third-party IP, and internal blocks.
• Own tape-out checklist and coordination across teams for clean handoff.
• Produce architecture specifications and interface control documents.
• Capture decisions and rationale to accelerate follow-on chip development.

Skills

SystemVerilog RTL design

Logic synthesis

Static timing analysis

CDC analysis

Verification coordination

IP integration

Tape-out ownership

Technical leadership

Written communication

AI productivity

Education

Electrical/Computer Engineering degree

Tools

Synopsys Design Compiler

Cadence Genus

PrimeTime/Tempus

VCS/Xcelium

Verdi/DVE

Job description

Micron Technology, Inc. is seeking a Principal Digital Design Engineer / Chip Lead to own chip architecture, lead RTL development, and drive timing closure for high-speed interfaces. You will manage tape-out processes with a small, senior team and collaborate with DV, analog, and PD peers to deliver a tape-ready design.

The role requires extensive SystemVerilog experience, strong synthesis/STA skills, and leadership capability. AI-assisted productivity is explicitly valued.