Chip Lead: Digital Design & RTL Architect

Micron Technology; Minneapolis (MN); On-site; USD 210,000 - 260,000; Full time

Job summary

Micron Technology is seeking a Principal Digital Design Engineer / Chip Lead to own core chip architecture, integrate hard macros with soft IP, and drive high-speed interface innovations from design to tape-out. You will lead a small, senior team spanning analog and digital disciplines and partner with DV to ensure robust verification and successful silicon release.

The role emphasizes hands-on layout, silicon characterization, and design verification, with opportunities to influence the next

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of ASIC/digital design experience with tape-out in a chip lead or senior role.
• Expert in SystemVerilog RTL design and coding best practices.

Responsibilities

• Define top-level chip architecture and integrate hard/soft IP.
• Own RTL design for all control blocks and top-level integration.
• Lead timing closure and define clocking and SDC budgets.
• Drive synthesis and optimize for PPA targets.
• Coordinate DV verification with assertion-based and coverage-driven methods.
• Define IP interfaces and manage vendor coordination.
• Own tape-out checklist and handoff to foundry.

Skills

SystemVerilog RTL

Synthesis tools

Timing analysis

CDC analysis

IP integration

Tape-out ownership

Verification coordination

Design documentation

Technical leadership

AI productivity

Education

B.S./M.S./PhD in Electrical/Computer Engineering

Tools

VCS/Xcelium

Verdi/DVE

Design Compiler

Genus

PrimeTime/Tempus

SpyGlass/JasperGold

Job description

Micron Technology is seeking a Principal Digital Design Engineer / Chip Lead to own core chip architecture, integrate hard macros with soft IP, and drive high-speed interface innovations from design to tape-out. You will lead a small, senior team spanning analog and digital disciplines and partner with DV to ensure robust verification and successful silicon release.

The role emphasizes hands-on layout, silicon characterization, and design verification, with opportunities to influence the next