Chip Lead: High-Speed Digital Design & Tape-Out

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 178,000 - 389,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Equity

Job summary

Micron Technology, Inc. seeks a Principal Digital Design Engineer / Chip Lead to own architecture, RTL design, and integration for high‑speed interface chips.

You will lead a small, senior team, drive timing closure, synthesis, and verification, coordinating with DV staff and IP blocks to tape out a next‑gen PHY solution. This role requires 10+ years of ASIC/digital design, expert SystemVerilog, and a proven tape‑out track record, with strong communication and leadership in a startup‑like

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of ASIC/digital design with at least one tape-out in a chip lead role.
• Expert-level SystemVerilog RTL design and coding best practices.

Responsibilities

• Define top-level chip architecture, partition hard/soft IP, and integrate hard macros with soft IP.
• Author, review, and maintain synthesizable SystemVerilog RTL for control blocks and top-level integration.
• Lead timing closure, create timing constraints, and guide constraints to Digital/Physical teams.
• Drive logic synthesis (DC/Genus) and optimize for PPA across all blocks.
• Coordinate DV with assertion-based and coverage-driven verification strategies.
• Define IP interfaces and manage integration agreements with vendors.

Skills

SystemVerilog RTL

Synthesis (DC/Genus)

Timing Closure

Static Timing Analysis

Assertion-based Verification

Tape-out Leadership

IP integration

Technical leadership

RTL Simulation

Cross-functional leadership

Education

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field

Tools

Synopsys Design Compiler

Cadence Genus

PrimeTime/Tempus

VCS/Xcelium

Verdi/DVE

SpyGlass/JasperGold

Job description

Micron Technology, Inc. seeks a Principal Digital Design Engineer / Chip Lead to own architecture, RTL design, and integration for high‑speed interface chips.

You will lead a small, senior team, drive timing closure, synthesis, and verification, coordinating with DV staff and IP blocks to tape out a next‑gen PHY solution. This role requires 10+ years of ASIC/digital design, expert SystemVerilog, and a proven tape‑out track record, with strong communication and leadership in a startup‑like