Chip Lead, Digital Design Architect – High-Speed Interfaces

Micron Technology, Inc; Richardson (TX); On-site; USD 178,000 - 389,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off

Paid holidays

Bonuses and equity

Job summary

Micron Technology, Inc. is seeking a Principal Digital Design Engineer / Chip Lead to own chip architecture, RTL design, timing, synthesis, and verification across a senior team.

You will drive integration of hard macros with soft IP and shepherd the design from architecture to tape-out. The role requires expert SystemVerilog RTL, strong leadership, and experience delivering high-speed interface circuits in a PHY-adjacent environment.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role.
• Expert-level proficiency in SystemVerilog RTL design and coding best practices.
• Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus).

Responsibilities

• Define top-level chip architecture and integrate hard macros with soft IP.
• Author and maintain synthesizable RTL for all IP control blocks and top-level integration.
• Lead timing closure and define clock domain crossing strategy.
• Drive logic synthesis and optimize for PPA targets across design blocks.
• Coordinate verification plans with DV teams and ensure coverage goals.
• Own tape-out checklist and cross-team coordination for clean tape-out handoff.

Skills

SystemVerilog RTL

Chip lead / technical leadership

Clocking/timing constraints

Verilog/VHDL debugging

Education

BS/MS/PhD in Electrical/Computer Engineering

Tools

Design Compiler/DC

Cadence Genus

PrimeTime/Tempus

VCS/Xcelium

Verdi/DVE

SpyGlass/JasperGold

Job description

Micron Technology, Inc. is seeking a Principal Digital Design Engineer / Chip Lead to own chip architecture, RTL design, timing, synthesis, and verification across a senior team.

You will drive integration of hard macros with soft IP and shepherd the design from architecture to tape-out. The role requires expert SystemVerilog RTL, strong leadership, and experience delivering high-speed interface circuits in a PHY-adjacent environment.