Staff ASIC Digital Design Engineer - High-Speed RTL

Micron Technology, Inc.; Minneapolis (MN); On-site; USD 150,000 - 256,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. in Minneapolis is seeking a Staff Engineer for ASIC Digital Design to lead the development of next-generation memory controllers and DRAM/NAND/SSD systems.

You will translate requirements into microarchitecture, own RTL development, and drive timing closure, verification, and silicon bring-up with cross-functional teams. Ideal candidates have 8+ years of experience in SystemVerilog, high-speed interfaces, and a strong grasp of analog/mixed-signal aspects.

Qualifications

• 8+ years of industry experience in ASIC/digital design.
• Strong SystemVerilog RTL coding and verification skills.
• Knowledge of high-speed IO crossings and ASIC flows.

Responsibilities

• Translate architectural requirements into microarchitecture and hardware.
• Lead digital designs interfacing with analog design, IP, and SystemVerilog blocks.
• Design RTL for DRAM/NAND/SSD controllers and systems.
• Own RTL development, simulation, synthesis, timing closure, formal verification, and silicon bring-up.
• Collaborate with Verification, Analog, Synthesis, and Physical Design teams.
• Contribute during chip bring-up and lab validation; develop HDL models.
• Provide technical leadership through design reviews and best practices.

Skills

SystemVerilog

RTL design

Verification techniques

Python

Linux scripting

Communication skills

Analog/mixed-signal understanding

DRAM interfaces

AI tools in ASIC flow

Generative AI in ASIC flow

Education

B.S./M.S./Ph.D. in Electrical Engineering

Tools

Synthesis tools

Linting tools

Formal verification tools

Gate-level validation

Job description

Micron Technology, Inc. in Minneapolis is seeking a Staff Engineer for ASIC Digital Design to lead the development of next-generation memory controllers and DRAM/NAND/SSD systems.

You will translate requirements into microarchitecture, own RTL development, and drive timing closure, verification, and silicon bring-up with cross-functional teams. Ideal candidates have 8+ years of experience in SystemVerilog, high-speed interfaces, and a strong grasp of analog/mixed-signal aspects.