Senior Digital ASIC Architect for Scientific Instruments

Brookhaven National Laboratory; New York (NY); On-site; USD 115,000 - 145,000; Full time

Job summary

Brookhaven National Laboratory in Upton, NY is seeking a Senior Digital ASIC Design Engineer to lead architecture, RTL, and integration of complex readout ASICs and SOCs for scientific instrumentation and high-energy physics experiments. You will collaborate with physicists, engineers, and firmware teams to deliver radiation-tolerant, low-power digital blocks for detector readout and timing distribution.

The role requires seven years of experience in digital ASIC design, SystemVerilog/Verilog

Qualifications

• Bachelor's degree in electrical engineering or closely related field.
• Minimum seven years of experience in digital ASIC design.
• Experience with SystemVerilog/Verilog for complex ASICs or SoC designs.
• Familiarity with CAD/EDA tools and interoperability across design, verification, synthesis, timing, and physical implementation.
• Excellent written and verbal communication skills for multidisciplinary teams.

Responsibilities

• Lead architecture, microarchitecture, RTL design, and integration of digital ASICs for detector readout and timing interfaces.
• Develop design specifications based on detector, data acquisition, timing, power, and radiation requirements.
• Design and implement synthesizable RTL in SystemVerilog/Verilog for data formatting, buffering, and high-speed interfaces.
• Coordinate with verification, physical design, and firmware teams to ensure tapeout readiness.
• Support FPGA prototyping, test-board development, and lab characterization of ASICs.

Skills

Digital ASIC design

SystemVerilog

Verilog

RTL design

Clocking & reset

Timing closure

Low-power design

Debugging large systems

Education

Bachelor's degree in electrical engineering or related field

Tools

Cadence

Synopsys

Siemens

ASIC flows

Job description

Brookhaven National Laboratory in Upton, NY is seeking a Senior Digital ASIC Design Engineer to lead architecture, RTL, and integration of complex readout ASICs and SOCs for scientific instrumentation and high-energy physics experiments. You will collaborate with physicists, engineers, and firmware teams to deliver radiation-tolerant, low-power digital blocks for detector readout and timing distribution.

The role requires seven years of experience in digital ASIC design, SystemVerilog/Verilog