Senior Digital-AMS RTL & Lab Integration Engineer

NXP Semiconductors; San Jose (CA); On-site; USD 166,000 - 229,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

401(k)

Paid leave

Job summary

NXP Semiconductors in California seeks a Senior Digital/AMS Design Engineer to drive RTL design and integration for automotive SerDes transceivers. You will own the RTL path through timing closure and support lab validation of the digital-analog wrapper.

HDL proficiency (SystemVerilog/Verilog), timing analysis, CDC handling, and Python or Perl scripting are required. You will work with analog front-ends and the verification team to ensure robust operation across PVT variations.

Qualifications

• BSEE/MSEE with 5–8+ years in Digital RTL Design or Digital Integration.
• HDL proficiency in SystemVerilog/Verilog for synthesis.
• Timing analysis, CDC, and SDC constraints mastery.
• Python or Perl for hardware control, test automation, data processing.
• Lab skills with logic analyzers and high-speed scopes; on‑chip debugging.
• Preferred: 10GBase-T, Automotive Ethernet, DFT/BIST, Verilog-A models.

Responsibilities

• RTL Design & Integration: develop and integrate RTL for control loops and high-speed data paths.
• Mixed-Signal Interface: define digital interfaces for ADCs, PLLs, and drivers.
• Timing Closure & Synthesis: lead digital path to meet timing in clock domains.
• Silicon Validation: collaborate on silicon bring‑up and real-time CSR verification.
• Functional Correctness: simulate block- and chip-level behavior across PVT variations.

Skills

RTL Design & Integration

SystemVerilog/Verilog

Python/Perl scripting

CDC/STA/Constraints

Lab Debugging

Automotive SerDes

Education

BSEE/MSEE

Tools

Verilog/SystemVerilog

JTAG/I2C/SPI

Job description

NXP Semiconductors in California seeks a Senior Digital/AMS Design Engineer to drive RTL design and integration for automotive SerDes transceivers. You will own the RTL path through timing closure and support lab validation of the digital-analog wrapper.

HDL proficiency (SystemVerilog/Verilog), timing analysis, CDC handling, and Python or Perl scripting are required. You will work with analog front-ends and the verification team to ensure robust operation across PVT variations.