Senior Digital/AMS Validation and Integration Engineer

NXP Semiconductors; San Jose (CA); On-site; USD 166,000 - 229,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

401(k)

Paid leave

Job summary

NXP Semiconductors in California seeks a Senior Digital/AMS Design Engineer to drive RTL design and integration for automotive SerDes transceivers. You will own the RTL path through timing closure and support lab validation of the digital-analog wrapper.

HDL proficiency (SystemVerilog/Verilog), timing analysis, CDC handling, and Python or Perl scripting are required. You will work with analog front-ends and the verification team to ensure robust operation across PVT variations.

Qualifications

• BSEE/MSEE with 5–8+ years in Digital RTL Design or Digital Integration.
• HDL proficiency in SystemVerilog/Verilog for synthesis.
• Timing analysis, CDC, and SDC constraints mastery.
• Python or Perl for hardware control, test automation, data processing.
• Lab skills with logic analyzers and high-speed scopes; on‑chip debugging.
• Preferred: 10GBase-T, Automotive Ethernet, DFT/BIST, Verilog-A models.

Responsibilities

• RTL Design & Integration: develop and integrate RTL for control loops and high-speed data paths.
• Mixed-Signal Interface: define digital interfaces for ADCs, PLLs, and drivers.
• Timing Closure & Synthesis: lead digital path to meet timing in clock domains.
• Silicon Validation: collaborate on silicon bring‑up and real-time CSR verification.
• Functional Correctness: simulate block- and chip-level behavior across PVT variations.

Skills

RTL Design & Integration

SystemVerilog/Verilog

Python/Perl scripting

CDC/STA/Constraints

Lab Debugging

Automotive SerDes

Education

BSEE/MSEE

Tools

Verilog/SystemVerilog

JTAG/I2C/SPI

Job description

We are seeking a Senior Digital/AMS Design Engineer to drive the integration of complex digital logic into our industry-leading Automotive SerDes transceivers. In this role, you will be responsible for the RTL design of the "Digital-Analog Wrapper", ensuring seamless control and data flow between high-speed analog front-ends and the DSP/Link-layer logic. You will own the path from RTL through timing closure and support the validation of that logic in the lab.

Key Responsibilities

• RTL Design & Integration: Develop and integrate RTL (Verilog/SystemVerilog) for control loops, calibration engines, and high-speed data paths in 10G+ transceivers.
• Mixed-Signal Interface: Define and implement the digital interface for analog blocks (ADCs, PLLs, Driver stages), ensuring robust signal crossing between asynchronous domains.
• Timing Closure & Synthesis: Lead the digital implementation flow, working closely with the physical design team to achieve timing closure in high-speed clock domains.
• Silicon Validation: (40% Lab Focus) Partner with the validation team to bring up silicon. Use Python-based tools to exercise RTL features, debug state machines, and verify registers (CSRs) in real-time hardware.
• Functional Correctness: Execute block-level and chip-level simulations to ensure digital control logic correctly handles analog PVT variations and startup sequences.

Skills & Qualifications

• Education: BSEE/MSEE with 5–8+ years of experience in Digital RTL Design or Digital Integration.
• HDL Expertise: Advanced proficiency in SystemVerilog/Verilog for synthesis.
• Timing & Implementation: Strong understanding of Static Timing Analysis (STA), clock domain crossing (CDC), and constraints (SDC).
• Scripting & Automation: Deep experience with Python or Perl for hardware control, test automation, and data processing.
• Lab Skills: Proficient in using logic analyzers, high-speed scopes, and JTAG/I2C/SPI protocols for on-chip debugging.
• Preferred Experience: Experience with 10GBase-T, ASA, or Automotive Ethernet standards. Familiarity with the hand-off between digital logic and high-speed Analog Front Ends (AFE). Knowledge of DFT (Design for Test) and BIST (Built-In Self-Test) insertion for high-speed links. Able to create Verilog-A models.

Salary & Benefits

• Base salary range: $166,200 to $228,500 annually (California).
• Competitive benefits, incentive compensation, and/or equity for certain roles.
• Health, dental, and vision insurance.
• 401(k).
• Paid leave.

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

The base salary range for this position is as mentioned below per year.

Thank you for considering a career at NXP.

#LI-6692 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.