Senior DFT Engineer – SoC Test & Silicon Validation

Arm Limited; Austin (TX); Hybrid; USD 198,000 - 268,000; Full time

Benefits offered by this job

Accommodations during recruitment

Job summary

Arm is seeking a Staff DFT Engineer in Austin to architect and implement DFT techniques for SOCs and sub-systems. You will insert DFT logic, validate with industry tools, and drive timing and ATPG coverage across RTL and gate-level simulations.

The role requires 10+ years in DFT, expertise with Cadence/Synopsys tools, Verilog RTL, and scripting. A hybrid work approach in a modern, innovative environment supports constant learning and impact.

Qualifications

• Bachelor/Master in Electronic or Computer Engineering.
• Staff DFT Engineer with 10+ years in Design for Test.
• Experience with Verilog RTL, TCL and/or Perl.
• Experience with Cadence and/or Synopsys DFT and simulation tools.

Responsibilities

• Architect, implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Insert DFT logic into SoC and sub-system level and validate features with standard simulation tools.
• Run RTL and timing-annotated gate-level simulations.
• Generate ATPG patterns and debug coverage to meet targets.
• Develop and validate design-for-test timing requirements and fixes.
• Collaborate with multi-functional teams for DFT RTL insertion, synthesis, scan insertion, PnR, and STA.
• Participate in ATE targeted test patterns, validation and silicon-debug.
• Collaborate on silicon characterization and validation with Test and product engineering.

Skills

DFT techniques

Verilog RTL

ATPG

Cadence tools

Synopsys tools

TCL/Perl scripting

Education

Bachelor's or Master's in Electronic/Computer Engineering

Tools

Siemens DFT tools

SSN

JTAG/IJTAG

Memory BIST

Job description

Arm is seeking a Staff DFT Engineer in Austin to architect and implement DFT techniques for SOCs and sub-systems. You will insert DFT logic, validate with industry tools, and drive timing and ATPG coverage across RTL and gate-level simulations.

The role requires 10+ years in DFT, expertise with Cadence/Synopsys tools, Verilog RTL, and scripting. A hybrid work approach in a modern, innovative environment supports constant learning and impact.