Staff DFT Engineer — Hybrid SoC Test & ATPG Lead

Arm; Austin (TX); Hybrid; USD 198,000 - 268,000; Full time

Job summary

Arm’s Solutions group DFT team is hiring in San Jose and Austin. We seek a Staff DFT Engineer to architect, implement, and validate advanced DFT techniques for SOCs and subsystems, working with RTL, timing, and silicon test teams. The role involves collaboration across RTL, physical implementation, and test engineering, with a hybrid work model.

Salary ranges from $198,100 to $268,000 per year. Accommodations and equal opportunity employment are noted; relocate and hybrid-remote options are

Qualifications

• Bachelor's or Master's degree in Electronic Engineering, Computer Engineering, or a related field.
• Staff DFT Engineer with 10+ years of experience in Design for Test.
• Core DFT skills include Siemens DFT tools, SSN, scan insertion, memory BIST, logic BIST, JTAG/IJTAG, ATPG, fault simulation, silicon debug.

Responsibilities

• Architect, implement, and validate innovative DFT techniques on SOCs and sub-systems.
• Insert DFT logic into SoC and sub-system level and validate all DFT features using industry standard simulation tools.
• Run RTL and timing annotated gate-level simulations and generate ATPG patterns.

Skills

Verilog RTL

ATPG

TCL/Perl scripting

Silicon debug

Education

Bachelor's or Master's degree in Electronic/Computer Engineering

Tools

Cadence

Synopsys DFT tools

Siemens DFT tools

SSN (Streaming Scan Network)

JTAG/IJTAG

Memory BIST

Job description

Arm’s Solutions group DFT team is hiring in San Jose and Austin. We seek a Staff DFT Engineer to architect, implement, and validate advanced DFT techniques for SOCs and subsystems, working with RTL, timing, and silicon test teams. The role involves collaboration across RTL, physical implementation, and test engineering, with a hybrid work model.

Salary ranges from $198,100 to $268,000 per year. Accommodations and equal opportunity employment are noted; relocate and hybrid-remote options are