DFT Engineer | Semiconductor | Onsite – Austin

Mogi I/O : OTT/Podcast/Short Video Apps for you; Austin (TX); On-site; USD 170,000 - 200,000; Full time

Job summary

A well-funded hardware startup is looking for an experienced DFT Engineer to drive innovative design-for-test methodologies for digital SoCs. This hands-on role involves collaboration to define and implement DFT strategies for next-generation DSP chips at the forefront of AI and cloud infrastructure. Ideal candidates will have extensive DFT experience and problem-solving skills, and will work onsite in Austin, Texas.

Qualifications

• 5+ years in DFT spec, architecture, insertion, and analysis for complex silicon.
• Experience in silicon bring-up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG.
• ASIC DFT, synthesis, simulation/verification know-how.

Responsibilities

• Lead and implement SoC DFT architecture and ATPG/MBIST strategy.
• Insert, validate, and debug all DFT logic.
• Own silicon bring-up and ATE debug for new test features.

Skills

DFT Specification & Architecture

ATPG

MBIST

JTAG

Silicon Bring‑up & Test (ATE)

Problem‑Solving

Communication

Education

Master’s degree in Electrical Engineering

Tools

DFT Max

Tessent

Modus

SpyGlass

TestKompress

Design/Fusion Compiler

Job description

Location

Austin, Texas (Onsite, 5 days/week)

Industry

Semiconductor, AI Infrastructure, Cloud Hardware

Salary

$170,000–$200,000 USD + Equity (4-year vesting)

Visa

H1‑B sponsorship available

Skills

• DFT Specification & Architecture, ATPG, MBIST, JTAG, Silicon Bring‑up & Test (ATE), Scan Chains, DFT Compression, Logic BIST, EDA Test Tools (DFT Max, Tessent, Modus, SpyGlass, Design/Fusion Compiler, TestKompress)
• IP Integration, ASIC Synthesis & Verification, Problem‑Solving, Communication

Summary

Well‑funded hardware startup (with $180MM in recent funding, backed by leading VCs) seeks an experienced DFT Engineer to innovate and own design‑for‑test (DFT) methodologies for advanced digital and mixed‑signal SoCs. This hands‑on role collaborates cross‑functionally to define, implement, and deploy robust DFT strategies for next‑generation programmable DSP chips powering the world’s fastest AI and cloud infrastructure.

Must‑Haves / Qualifications

• 5+ years in DFT spec, architecture, insertion, and analysis for complex silicon
• Experience in silicon bring‑up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG
• ASIC DFT, synthesis, simulation/verification know‑how
• Strong organizational/problem‑solving skills; detail oriented
• Willing to work on‑site in Austin, TX (relocation not covered)

Preferred

• Master’s degree in Electrical Engineering
• IP integration (memories, test controllers, MBIST, TAP)
• Expert use of EDA tools: DFT Max, Tessent, Modus, Design/Fusion Compiler, SpyGlass, TestKompress; Silicon test coverage improvement, hierarchical design/test

Responsibilities

• Lead and implement SoC DFT architecture and ATPG/MBIST strategy
• Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST
• Own silicon bring‑up and ATE debug for new test features and DFT IP
• Collaborate to improve test coverage, resolve RTL violations, and streamline test processes
• Develop and maintain formal DFT documentation

Seniority level

Mid‑Senior level

Employment type

Full‑time

Job function

Engineering and Information Technology