Senior DfT Engineer — RTL & Testability Architect

NXP Semiconductors; Chandler (AZ); On-site; USD 110,000 - 150,000; Full time

Job summary

NXP Semiconductors is seeking a DfT engineer in Chandler, AZ. You will work with an experienced team to define and implement testability for complex analog/mixed-signal IPs and digital logic.

Expect collaboration across design, test, quality, and validation teams to ensure robust DfT architectures. The role requires a Master’s degree in electrical engineering or a related field and 3+ years of relevant experience, with willingness to relocate to the Phoenix metro area and be on-site at least

Qualifications

• Master's degree (MSEE) with courses in Digital Design, RTL coding, DfT, Computer Architecture, Digital Verification
• 3 years of experience in a similar DfT, Digital Design & Architecture role
• Willing to relocate to Phoenix Metro area (AZ) and be on-site in Chandler at least 3 days per week

Responsibilities

• Collaborate with Product Definer, Analog/Digital Design Leads, Test Lead, Product Engineer, Quality Engineer, Validation Engineer to define testability requirements
• Develop DfT for analog/mixed-signal IPs, RAM/ROM/NVM, ADC/DAC and digital logic
• Produce high-quality RTL design using Verilog and SystemVerilog
• Define Verification Plan for features and write tests; validate at Chiptop DV environment
• Perform scan insertion, optimization, length balancing, P&R-aware rerouting, Test-Point insertion, ATPG patterns
• Support Test Engineers during silicon debugging and customer returns
• Participate in Design & Test Review meetings and create DfT architecture/design docs
• Troubleshoot DfT issues through development lifecycle and stay updated with industry trends

Skills

Verilog

SystemVerilog

DfT

Digital Design

RTL coding

Education

Master's degree in E.E. or related field

Tools

ATPG

EDA tools

Job description

NXP Semiconductors is seeking a DfT engineer in Chandler, AZ. You will work with an experienced team to define and implement testability for complex analog/mixed-signal IPs and digital logic.

Expect collaboration across design, test, quality, and validation teams to ensure robust DfT architectures. The role requires a Master’s degree in electrical engineering or a related field and 3+ years of relevant experience, with willingness to relocate to the Phoenix metro area and be on-site at least