Senior DFT Design Engineer – Automotive PMICs

Renesas Electronics; Chandler (AZ); On-site; USD 120,000 - 170,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas Electronics in Chandler, AZ, is seeking an experienced digital design/DFT engineer to join its automotive PMIC team. You will design, test, and validate scan and DFT patterns across RTL Verilog/SystemVerilog, working with cross-functional teams.

The role requires 12+ years (Master’s) or 15+ years (Bachelor’s) in digital design/DFT, hands-on ATPG/Logicbist, and strong collaboration; automotive ASIL experience is preferred, with on-site work three days a week.

Qualifications

• Master’s plus 12+ years or Bachelor’s plus 15+ years experience in digital design and DFT implementation.
• Must be a team player and yet be an independent thinker with strong digital design and DFT fundamentals.
• Hands on experience in Scan insertion, improving scan coverage, ATPG, experience in Logicbist insertion during synthesis or rtl.
• Gate level simulations with test patterns, delivering test patterns to Test engineering team and work closely with them to get the patterns validated.
• Must have basic digital RTL coding experience besides synthesis exposure.
• Must have experience with at least 8 tapeouts with hands on experience with DFT/Scan.
• Ideal candidate will have solid understanding of synthesizable design, timing constraints and exceptions.
• Must have experience with industry standard Synopsys, Cadence, Mentor, Siemens for scan, Lbist insertion and ATPG. Tetramax experience is a huge plus.
• Attention to detail, accuracy and expertise in DFT required.
• Must have good written and verbal cross-functional communication skills
• Have an analytical mind - be open to new ideas and have capability to persuade others inconvincing and implementing better flows and processes.
• Mixed signal experience highly preferred.
• Exposure to automotive test requirements, ASIL, is highly preferred.

Responsibilities

• Inserting DFT/Scan on digital logic, ATPG, validating test patterns on pre and post layout gate level netlist.
• Delivering test patterns to TEST engineering team and validating them on silicon.
• Inserting Logicbist with industry standard tools.
• Improving scan coverage and modifying RTL for scan.
• Reduce ATE tester time by reducing scan patterns while achieving the required coverage.
• Participate in all aspects of digital design flow - Micro-architecture, Design partitioning, RTL Verilog / System Verilog coding, DFT insertion, generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC.
• Working closely with Architects, Design, P&R, Test and Silicon validation teams.
• Assisting with top level test-bench creation for scan and running gate level simulations.
• Debug scan pattern fails on ATE and fix the scan patterns.
• Writing detailed design documents and help writing DFT specifications, reviewing the specs with different stake holders and own the design to meet the spec.
• Organizing and participating in key design reviews and completion of various checklists.

Skills

digital design

DFT/ATPG

Logicbist

RTL Verilog

SystemVerilog

Synthesis

Timing Constraints

test patterns

gate level simulations

P&R interaction

design reviews

Education

Master’s degree in Electrical Engineering

Bachelor’s degree in Electrical Engineering

Tools

Synopsys

Cadence

Mentor

Siemens

Tetramax

Job description

Renesas Electronics in Chandler, AZ, is seeking an experienced digital design/DFT engineer to join its automotive PMIC team. You will design, test, and validate scan and DFT patterns across RTL Verilog/SystemVerilog, working with cross-functional teams.

The role requires 12+ years (Master’s) or 15+ years (Bachelor’s) in digital design/DFT, hands-on ATPG/Logicbist, and strong collaboration; automotive ASIL experience is preferred, with on-site work three days a week.