Senior DfT Engineer

NXP Semiconductors; Chandler (AZ); On-site; USD 110,000 - 150,000; Full time

Job summary

NXP Semiconductors is seeking a DfT engineer in Chandler, AZ. You will work with an experienced team to define and implement testability for complex analog/mixed-signal IPs and digital logic.

Expect collaboration across design, test, quality, and validation teams to ensure robust DfT architectures. The role requires a Master’s degree in electrical engineering or a related field and 3+ years of relevant experience, with willingness to relocate to the Phoenix metro area and be on-site at least

Qualifications

• Master's degree (MSEE) with courses in Digital Design, RTL coding, DfT, Computer Architecture, Digital Verification
• 3 years of experience in a similar DfT, Digital Design & Architecture role
• Willing to relocate to Phoenix Metro area (AZ) and be on-site in Chandler at least 3 days per week

Responsibilities

• Collaborate with Product Definer, Analog/Digital Design Leads, Test Lead, Product Engineer, Quality Engineer, Validation Engineer to define testability requirements
• Develop DfT for analog/mixed-signal IPs, RAM/ROM/NVM, ADC/DAC and digital logic
• Produce high-quality RTL design using Verilog and SystemVerilog
• Define Verification Plan for features and write tests; validate at Chiptop DV environment
• Perform scan insertion, optimization, length balancing, P&R-aware rerouting, Test-Point insertion, ATPG patterns
• Support Test Engineers during silicon debugging and customer returns
• Participate in Design & Test Review meetings and create DfT architecture/design docs
• Troubleshoot DfT issues through development lifecycle and stay updated with industry trends

Skills

Verilog

SystemVerilog

DfT

Digital Design

RTL coding

Education

Master's degree in E.E. or related field

Tools

ATPG

EDA tools

Job description

As a DfT engineer, you will join a highly experienced team.

Key Responsibilities

1. Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product Engineer, Quality Engineer, Validation Engineer – to identify the superset of requirements for Testability of the chip (Functional mode, Debug mode, ATPG).
2. Gain deep understanding on existing and innovative ways to insert DfT for complex analog and mixed-signal IPs, standard Macros (RAM, ROM, NVM, ADC, DAC) and complex digital logic.
3. High-quality of RTL design using Verilog and System-Verilog
4. Define Verification Plan for the implemented features and write tests, debug and get those passing at Chiptop level DV environment
5. Scan insertion, optimization, length balancing, P&R-aware rerouting of chains, Test-Point insertion, ATPG patterns generation, simulation and debug
6. Support Test Engineers during debug of patterns on new silicon, and on customer returns
7. Participate in Design & Test Review meetings and support the team for DfT
8. Generate comprehensive DfT Architecture & Design documentation and maintain it to match later updates
9. Troubleshoot and resolve issues related to DfT throughout the development lifecycle
10. Stay updated with the latest industry trends, tools, and methodologies in DfT design

Job Qualification

Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL coding, DfT, Computer Architecture, Digital Verification. Minimum 3 years of experience in similar role of DfT, Digital Design & Architecture. Seeking 3-8 years total experience for this role Willing to relocate to Phoenix Metro area (Arizona) and minimum 3 days per week full-day presence in NXP's Chandler office Excellent on problem-solving, teamwork, planning, organizing, attention to detail and communication skills.

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

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