Senior DFT Engineer | California (Onsite)

MosChip Technologies Limited; Santa Clara (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

MosChip Technologies Limited is seeking a Senior DFT Engineer in the Bay Area, CA to support the implementation and verification of DFT solutions across the full flow from scan to silicon bring-up. The role requires hands-on experience with MBIST, JTAG, and Memory Repair, plus strong collaboration with design teams.

Candidates should have 3–8 years of DFT experience, proficiency with Tessent/EDA tools, and scripting in TCL/Perl.

Qualifications

• 3-8 years of experience in DFT for SoC/ASIC designs
• Experience with Scan, Compression, ATPG, JTAG and Boundary Scan
• Hands-on MBIST implementation/verification and Memory Repair (BIRA/BISR)
• Experience with hierarchical SoC DFT implementation and verification
• Familiarity with DFT simulations, SDF timing simulations and debugging timing constraints
• Experience with Tessent EDA tools and related suites
• Scripting skills in TCL and/or Perl
• Experience with tape-outs, preferably at 5nm or below
• Strong debugging, problem-solving, communication and teamwork skills

Responsibilities

• Support implementation and verification of DFT solutions for complex SoC/ASIC designs.
• Work across full DFT flow from scan implementation through ATPG, MBIST and silicon bring-up.
• Collaborate with design and verification teams to ensure DFT robustness and testability.

Skills

DFT for SoC/ASIC designs

Scan & Boundary Scan

ATPG

MBIST & Memory Repair

Hierarchical SoC DFT

Timing/debugging

Scripting TCL/Perl

Tape-out experience

Teamwork & communication

Debugging

Tools

Siemens Tessent

Synopsys tools

Cadence tool suites

Job description

3-8 Years

Full-Time

We are looking for a Senior DFT Engineer to support the implementation and verification of DFT solutions for complex SoC/ASIC designs. The ideal candidate will have hands‑on experience across the full DFT flow, from scan implementation through ATPG, MBIST, and silicon bring‑up activities.

Key Requirements:

• 3 to 8 years of experience in DFT for SoC/ASIC designs
• Strong experience with Scan, Compression, ATPG, JTAG, and Boundary Scan
• Hands‑on experience with MBIST implementation, verification, and Memory Repair (BIRA/BISR)
• Experience with hierarchical SoC DFT implementation and verification
• Familiarity with DFT simulations, SDF timing simulations, and debugging timing constraints
• Experience with industry‑standard DFT tools such as Siemens Tessent, Synopsys, or Cadence tool suites
• Scripting skills in TCL and/or Perl
• Experience with successful SoC/ASIC tape outs, preferably at advanced technology nodes (5nm or below)
• Strong debugging, problem‑solving, communication, and teamwork skills
• Experience with Tessent EDA tools is a must

Location:

Bay Area, CA