Senior DFT Engineer – Multi-Die SoC Test Architecture

DensityAI; Mountain View (CA); On-site; USD 300,000 - 350,000; Full time

Benefits offered by this job

Equity grant

Medical/Dental/Vision

401(k)

Standard PTO

Job summary

DensityAI is seeking an experienced Design-for-Test (DFT) Engineer to join our silicon engineering team in Mountain View, California. In this critical role, you will build and advance the DFT function, collaborating across various teams to ensure high-quality silicon. Ideal candidates will have 7+ years of hands-on experience in DFT engineering, with expertise in all facets of the discipline.

The position includes comprehensive responsibilities such as architecture, verification, and silicon bring-up, as well as working with advanced packaging technologies.

Qualifications

• 7+ years of hands-on DFT engineering on complex digital SoC/ASIC designs.
• Breadth across all of DFT — architecture, insertion, ATPG, BIST, boundary scan, verification, and silicon test.
• Gate-level simulation of test modes and DFT pattern verification.

Responsibilities

• Build out and advance the DFT flow—insertion, pattern generation, verification, and signoff.
• Implement and verify Memory BIST and support silicon bring-up and diagnosis.
• Collaborate with physical design on scan stitching, test point insertion, and timing.

Skills

DFT engineering

Scan insertion

ATPG

Boundary scan

Verilog/SystemVerilog

Python scripting

Education

BS/MS in Electrical Engineering, Computer Engineering, or related field

Tools

Siemens Tessent

Job description

DensityAI is seeking an experienced Design-for-Test (DFT) Engineer to join our silicon engineering team in Mountain View, California. In this critical role, you will build and advance the DFT function, collaborating across various teams to ensure high-quality silicon. Ideal candidates will have 7+ years of hands-on experience in DFT engineering, with expertise in all facets of the discipline.

The position includes comprehensive responsibilities such as architecture, verification, and silicon bring-up, as well as working with advanced packaging technologies.