Senior DFT Engineer — Leading Silicon Testing (Equity)

Thomas To; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Comprehensive benefits package

Job summary

NVIDIA is seeking an experienced Design-For-Test (DFT) engineer in Santa Clara to advance test methodologies for next-generation silicon. You will collaborate with EDA vendors and CAD teams to shape scalable, automated test flows and co-architect novel DFT strategies with VLSI and product engineering.

You will own the full ATPG lifecycle from verification to pattern generation and ATE bring-up, mentor junior engineers, and help scale technical excellence across the team.

Qualifications

• MS/PhD or equivalent experience in Electrical Engineering or a related field.
• 6+ years of hands-on experience in Design-For-Test (DFT).
• Deep knowledge of DFT tools, methodologies, and test strategies for complex, large-scale designs.
• Strong experience with industry standard ATPG tools.
• Clear, effective communicator—strong written and verbal skills.
• Passion for mentoring and scaling technical excellence in a team.

Responsibilities

• Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms.
• Collaborate with leading EDA vendors to shape tool capabilities that meet NVIDIA’s ambitious design goals, and partner with internal CAD teams to drive scalable, automated solutions.
• Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation.
• Own the full ATPG lifecycle—verification, coverage analysis, pattern generation, and ATE bring-up—across NVIDIA’s full product portfolio.
• Guide and mentor junior engineers, helping them navigate complex design trade-offs to achieve world-class quality and efficiency.

Skills

DFT

ATPG tools

Mentoring

Communication

VLSI/ASIC understanding

Education

MS/PhD in Electrical Engineering or related field

Tools

DFT tools

ATP G tools

EDA tool flows

Job description

NVIDIA is seeking an experienced Design-For-Test (DFT) engineer in Santa Clara to advance test methodologies for next-generation silicon. You will collaborate with EDA vendors and CAD teams to shape scalable, automated test flows and co-architect novel DFT strategies with VLSI and product engineering.

You will own the full ATPG lifecycle from verification to pattern generation and ATE bring-up, mentor junior engineers, and help scale technical excellence across the team.