DFT Engineer

Avinyaa Technologies, LLC.; Sunnyvale (CA); On-site; USD 83,000 - 90,000; Full time

Job summary

QFocus Technologies in Sunnyvale, CA seeks a DFT Engineer to define and execute robust DFT strategies for high‑performance SoCs/ASICs. You will work with front-end design, physical design, verification, and product engineering to ensure high test coverage and streamlined post‑silicon test enablement.

Key responsibilities include implementing DFT architectures (Scan, ATPG, MBIST, IJTAG), performing scan insertion and optimization, and integrating MBIST controllers.

Qualifications

• 3+ years hands-on DFT experience in advanced SoC/ASIC development.
• Verilog/SystemVerilog proficiency for DFT integration and simulation debugging.
• Scan synthesis and boundary scan integration experience.
• ATPG pattern generation, debugging, and fault-grading experience.
• MBIST architecture and memory repair experience.
• Knowledge of IEEE 1149.1/JTAG and related test logic.

Responsibilities

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG (IEEE 1149.1/1500/1687 IJTAG).
• Perform Scan Chain Insertion, stitching, and optimization for timing closure and power grid compatibility.
• Integrate MBIST controllers, repair mechanics, and memory test routines.
• Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware).
• Execute Verilog/SystemVerilog simulations for gate-level DFT validation with SDF timing.
• Run DFT linting using SpyGlass DFT, Tessent, Modus, or TetraMAX.
• Translate ATPG/MBIST patterns to tester formats (WGL/STIL) for ATE deployment.
• Support post-silicon bring-up and pattern conversion, debugging silicon failures.
• Collaborate with Product and Test Engineering to optimize test time and yield.

Skills

Verilog/SystemVerilog

DFT

ATPG

MBIST

JTAG

Scan Insertion

Scripting (Python/Tcl)

Synthesis/STA tools

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Job description

Pay Rate: around/ within $ 65/ Hr. C2C / $60/hr W2

Duration: long-term

Exp. Level: 5 to 15 Yrs,

Skills & Description:

Position Overview

As a DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will work closely with front-end design, physical design, verification, and product engineering teams to ensure high test coverage, optimal silicon quality, and streamlined post-silicon manufacturing test enablement.

Key Responsibilities

Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST,and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).

Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.

Integrate Memory BIST (MBIST) controllers, repair mechanics, and custom memorytest routines.

Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, includingStuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.

Execute Verilog/System Verilog simulations for gate-level DFT validation, ensuring timingand vector cleanliness (SDF simulation).

Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT,Tessent, Modus, or TetraMAX)

Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) forATE (Automatic Test Equipment) deployment.

Support post-silicon bring-up in the lab, debugging first-silicon DFT features, patternconversion, and silicon failures.

Collaborate with Product and Test Engineering (PTE) teams to optimize test time,diagnose failure modes, and boost manufacturing yield.

Required Qualifications

Experience: 3+ years of hands-on DFT experience in advanced SoC/ASIC developmentnodes.

Core Skills & Technical Expertise: Verilog / SystemVerilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.

Scan Insertion: Hands-on experience with scan synthesis, compressed scanarchitectures (EDT/SmartTest), and boundary scan integration.

ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.

MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.

JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.

Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.

Preferred Skills

Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.

Knowledge of advanced DFT concepts like High-Speed IO testing, SerDes loopback, or Analog DFT.

Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes

Best regards,

Office: [phone] Ext: 1001

LinkedIn: https://www.linkedin.com/in/manisha-karmakar-%F0%9F%A7%BF-57717310a/