Senior DFT Engineer for AI Accelerator Tapeout

Nexus Semiconductor Recruitment; United States; On-site; USD 180,000 - 260,000; Full time

Job summary

Nexus Semiconductor Recruitment is supporting a fast-growing semiconductor company developing next-generation AI inference accelerators, looking to hire a Senior DFT Engineer. This hands-on role has end-to-end ownership from DFT architecture through tapeout and first silicon.

You will own scan, ATPG, compression, MBIST, boundary scan and IJTAG, drive DFT integration and coverage, and collaborate with RTL, Physical Design and silicon validation to ensure robust test solutions.

Qualifications

• 8+ years of ASIC/DFT experience with multiple tapeouts.
• Experience with complex, high-performance SoCs.
• AI accelerators, HBM, PCIe, chiplets or advanced nodes desirable.

Responsibilities

• Own DFT architecture through tapeout and first silicon.
• Drive DFT integration, verification and coverage closure.
• Work closely with RTL, Physical Design and silicon validation.
• Support test architecture, timing closure and post-silicon debug.

Skills

DFT engineering

ATPG

MBIST

Boundary scan

IJTAG

SystemVerilog

SoC design

Tapeout experience

Tools

Tessent

Job description

Nexus Semiconductor Recruitment is supporting a fast-growing semiconductor company developing next-generation AI inference accelerators, looking to hire a Senior DFT Engineer. This hands-on role has end-to-end ownership from DFT architecture through tapeout and first silicon.

You will own scan, ATPG, compression, MBIST, boundary scan and IJTAG, drive DFT integration and coverage, and collaborate with RTL, Physical Design and silicon validation to ensure robust test solutions.