Senior DFT & Test Architect for AI/SoC

Tenstorrent; Austin, Fort Collins, Santa Clara (TX, CO, CA); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Design for Test (DFT) specialist to lead DFT features across high-performance ASIC/SoC designs. You will work on RTL-to-tapeout, implementing scan, JTAG, compression, MBIST, and related DFx techniques with a team of experienced engineers.

The role is hybrid, based in the United States at Santa Clara, CA or Austin, TX or Fort Collins, CO. The company emphasizes collaboration, growth, and cutting-edge AI hardware solutions.

Qualifications

• BS/MS/PhD in EE/ECE/CE/CS with 5+ years experience in DFx/DFT.
• Fluent in Verilog RTL for DFT logic and comfortable with SystemVerilog/UVM.
• Hands-on experience with ATPG and DFx insertion tools, fault models, and low-power design flows.
• Strong debug and problem-solving skills across design hierarchies and collaboration with cross-functional teams.

Responsibilities

• Implement and integrate DFT features (scan, JTAG, compression, ASST, MBIST) into RTL from early design through tapeout across multiple IPs.
• Own ATPG, test coverage analysis, and gate-level simulation (e.g., with Synopsys VCS/Verdi) to achieve and maintain high-quality test coverage.
• Plan, implement, and verify MBIST, and work closely with Test Engineering on test planning, pattern delivery, and debug.
• Develop and refine DFx flows and methodology that integrate cleanly with front-end and physical design flows, balancing coverage, test cost, and design intrusiveness.

Skills

Verilog RTL

SystemVerilog/UVM

ATPG

DFx insertion tools

Fault models

Low-power design flows

Debugging

Education

BS/MS/PhD in EE/ECE/CE/CS

Tools

Synopsys VCS

Synopsys Verdi

Job description

Tenstorrent is seeking a Design for Test (DFT) specialist to lead DFT features across high-performance ASIC/SoC designs. You will work on RTL-to-tapeout, implementing scan, JTAG, compression, MBIST, and related DFx techniques with a team of experienced engineers.

The role is hybrid, based in the United States at Santa Clara, CA or Austin, TX or Fort Collins, CO. The company emphasizes collaboration, growth, and cutting-edge AI hardware solutions.