Senior ASIC Design Engineer - DFX with Impact & Equity

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 168,000 - 310,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior ASIC Design Engineer – DFX to lead fuse controller and DFT IP architecture for cutting-edge SoCs. You will develop scalable DFT methods and collaborate with architects, platform, and software teams to define feature sets.

You will mentor junior engineers, support post-silicon bring-up, and contribute to test plans and validation. The role rewards deep technical curiosity, teamwork, and solving complex challenges in a fast-paced semiconductor environment.

Qualifications

• 8+ years in SoC architecture, RTL design, and verification
• 5+ years of hands-on SoC architecture, RTL design and verification
• Proficiency in Verilog; UVM experience a plus
• Deep expertise in DFT design, methodology, and implementation
• Familiarity with clocking, STA, placement & routing, and power optimization
• Post-silicon bring-up on ATE, pattern formats, test program development, failure analysis
• Python, Perl, and Tcl scripting proficiency
• Excellent communication and collaborative mindset

Responsibilities

• Own the architecture and design of fuse controller and other DFT IPs for SoCs
• Develop, deploy, and enhance DFT methodologies for scalability
• Define and align feature sets with architects, platform, and software teams
• Partner with design, verification, synthesis, timing, and backend teams for cohesive integration
• Create and execute test plans for functional and full-chip DFT verification
• Support post-silicon bring-up and validation including debugging
• Mentor junior engineers on test design strategies and trade-offs

Skills

Verilog RTL

Python scripting

DFT methodology

SoC architecture

Communication skills

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

UVM

Tcl scripting

Perl scripting

Job description

NVIDIA is seeking a Senior ASIC Design Engineer – DFX to lead fuse controller and DFT IP architecture for cutting-edge SoCs. You will develop scalable DFT methods and collaborate with architects, platform, and software teams to define feature sets.

You will mentor junior engineers, support post-silicon bring-up, and contribute to test plans and validation. The role rewards deep technical curiosity, teamwork, and solving complex challenges in a fast-paced semiconductor environment.