DFT Methodology Engineer: Advanced SoC Testing & Validation

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA is seeking a DFT Methodology Engineer to own cross-functional DFT design and deployment across next‑generation SoCs. You will lead testing approaches including TAP, scan, memory BIST, and DFX security, partnering with RTL, timing, and physical design teams.

The role demands a Master’s in Electrical Engineering and 10+ years in SoC architecture, RTL design, and verification. Base salary ranges and equity opportunities accompany a comprehensive benefits package.

Qualifications

• Master’s degree (or equivalent experience) in Electrical Engineering or related field.
• 10+ years of hands-on experience in SoC architecture, RTL design, and verification.
• Excellent analytical skills in verification and validation of test patterns and logic on complex multi-million gate designs.

Responsibilities

• Own and work with cross-functional teams, implementing state-of-the‑art designs in test access mechanisms and DFT architectures.
• Architect, develop and deploy DFT methodologies for next-generation products including RTL design, verification and pattern generation.
• Mentor junior engineers on test designs and trade-offs including cost and quality.

Skills

DFT architecture

RTL design

Verification

Memory BIST

Scan design

DFX security

Mentoring

Cross-functional teamwork

Education

Master’s degree in Electrical Engineering

Job description

NVIDIA is seeking a DFT Methodology Engineer to own cross-functional DFT design and deployment across next‑generation SoCs. You will lead testing approaches including TAP, scan, memory BIST, and DFX security, partnering with RTL, timing, and physical design teams.

The role demands a Master’s in Electrical Engineering and 10+ years in SoC architecture, RTL design, and verification. Base salary ranges and equity opportunities accompany a comprehensive benefits package.