Senior DFT & ATPG Engineer for SoC/ASIC

Equitasitinc; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Equitasitinc is seeking an experienced DFT/ATPG engineer to lead verification afforded by scan-based testing for complex SoC/ASIC projects in the United States. You will drive ATPG pattern generation, diagnose failures, and optimize test architectures to ensure robust silicon products.

The role requires strong RTL knowledge, memory test architecture insight, and familiarity with industry standard DFT/ATPG EDA tools.

Qualifications

• 5+ years hands-on experience in DFT and ATPG for SoC/ASIC designs
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
• Proven expertise in ATPG pattern generation, analysis, and debug
• Experience with MBIST, including memory test architectures and diagnostics
• Knowledge of IO Test methodologies for interface and pin level validation
• Solid understanding of clock DFT and clock verification concepts
• Strong grasp of digital design and RTL fundamentals
• Experience with industry standard DFT/ATPG EDA tools
• Ability to work effectively in fast paced semiconductor programs
• Strong analytical, problem solving, and communication skills

Skills

DFT/ATPG

DFT fundamentals

ATPG pattern gen

MBIST

IO Test methods

Clock DFT

RTL fundamentals

DFT/ATPG EDA tools

Fast-paced environment

Analytical skills

Tools

DFT/ATPG EDA tools

Job description

Equitasitinc is seeking an experienced DFT/ATPG engineer to lead verification afforded by scan-based testing for complex SoC/ASIC projects in the United States. You will drive ATPG pattern generation, diagnose failures, and optimize test architectures to ensure robust silicon products.

The role requires strong RTL knowledge, memory test architecture insight, and familiarity with industry standard DFT/ATPG EDA tools.