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Equitasitinc is seeking an experienced DFT/ATPG engineer to lead verification afforded by scan-based testing for complex SoC/ASIC projects in the United States. You will drive ATPG pattern generation, diagnose failures, and optimize test architectures to ensure robust silicon products.
The role requires strong RTL knowledge, memory test architecture insight, and familiarity with industry standard DFT/ATPG EDA tools.