Senior DFT Architect: Lead Advanced SoC Test & Methodology

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 200,000 - 270,000; Full time

Job summary

Synopsys is seeking a senior DFT architect to design and deploy advanced DFT solutions for complex ASIC and SoC programs. You will guide test methodologies, advise customers, and drive scalable architectures across multiple engagements. The role emphasizes leadership, cross‑functional collaboration, and production-ready implementation.

A strong background in ATPG and IEEE standards is required. You will collaborate with R&D, product engineering, and strategic accounts to shape next‑gen test

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 18+ years in semiconductor or EDA with DFT, ATPG, manufacturing test.
• Experience architecting DFT solutions for large ASIC/SoC designs.
• Hands-on with Synopsys TestMAX DFT and TestMAX ATPG.
• Strong knowledge of scan insertion, compression, hierarchical DFT, and diagnosis.

Responsibilities

• Drive advanced DFT methodologies for complex ASIC/SoC programs across customer and internal engagements.
• Serve as a senior technical expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
• Lead deployment of advanced DFT architectures including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrappers.
• Architect scalable test access networks using IEEE 1149.1, 1149.6, 1687, and 1500 standards.
• Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
• Drive reusable methodologies, automation, and signoff criteria to improve deployment quality.
• Partner with R&D to influence product capabilities and methodology improvements.
• Mentor engineers and strengthen DFT expertise across the organization.

Skills

DFT architectures

ATPG

IEEE 1149.1

JTAG/IJTAG

Scripting (Python/Tcl)

RTL-to-GDSII flows

Leadership

Education

BS/MS in Electrical Engineering

Tools

Synopsys TestMAX

TestMAX ATPG

Job description

Synopsys is seeking a senior DFT architect to design and deploy advanced DFT solutions for complex ASIC and SoC programs. You will guide test methodologies, advise customers, and drive scalable architectures across multiple engagements. The role emphasizes leadership, cross‑functional collaboration, and production-ready implementation.

A strong background in ATPG and IEEE standards is required. You will collaborate with R&D, product engineering, and strategic accounts to shape next‑gen test