Senior DFT Engineer - SoC/ASIC Test Architect

MetAntz; San Francisco (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

QFocus Technologies in Sunnyvale, CA seeks a Senior DFT Engineer to define, architect, and execute robust DFT strategies for high‑performance SoCs and ASICs, collaborating with front‑end, physical design, verification, and product teams.

You will implement scan, ATPG, MBIST, and JTAG flows, optimize test coverage, support post‑silicon bring‑up, and drive test efficiency and silicon yield. Proficiency in Verilog/SystemVerilog and memory test techniques required.

Qualifications

• Experience defining and implementing DFT strategies for high‑performance SoCs/ASICs.
• Proficiency in Verilog/SystemVerilog and memory test techniques.
• Ability to collaborate across front-end, physical design, verification and product teams.

Responsibilities

• Define, architect and execute robust DFT strategies for complex SoCs/ASICs.
• Implement scan, ATPG, MBIST and JTAG flows and optimize test coverage.
• Support post‑silicon bring‑up and drive test efficiency and silicon yield.

Skills

DFT

Verilog/SystemVerilog

ATPG

MBIST

JTAG

Job description

QFocus Technologies in Sunnyvale, CA seeks a Senior DFT Engineer to define, architect, and execute robust DFT strategies for high‑performance SoCs and ASICs, collaborating with front‑end, physical design, verification, and product teams.

You will implement scan, ATPG, MBIST, and JTAG flows, optimize test coverage, support post‑silicon bring‑up, and drive test efficiency and silicon yield. Proficiency in Verilog/SystemVerilog and memory test techniques required.