Senior DFT Architect for LEO Satellite Chips

Amazon Kuiper Manufacturing Enterprises LLC; Encinitas (CA); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a DFT Engineer to define and implement design-for-test solutions for our LEO chip programs. You will work with ASIC teams across sites to integrate DFT logic such as MBIST, clock controls, and JTAG, while pushing automated scripts and AI-assisted flows to improve the DFT workflow.

The role requires a Bachelor's in Electrical/Communications Engineering and 5+ years of deep sub-micron DFT experience, with strong collaboration across RFIC and

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or related field.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT insertion and validation.

Responsibilities

• Architect and define DFT solutions tailored to various LEO chips.
• Improve and customize IPs and DFT methodology, leveraging AI flows.
• Collaborate with ASIC design teams across sites to integrate DFT logic (MBIST, clock controls, JTAG).
• Coordinate with RFIC teams to ensure high fault coverage on mixed-signal blocks.
• Ensure blocks meet DFT, timing, and power targets with implementation teams.
• Translate ATE patterns to tester formats with Test engineering.
• Assist test team in bringing up digital portions of LEO chips.

Skills

DFT techniques

Automation scripting

MBIST

JTAG controllers

Education

Bachelor's degree in Electrical/Communications Engineering

Tools

Automated DFT Insertion & Validation scripts

RFIC collaboration

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a DFT Engineer to define and implement design-for-test solutions for our LEO chip programs. You will work with ASIC teams across sites to integrate DFT logic such as MBIST, clock controls, and JTAG, while pushing automated scripts and AI-assisted flows to improve the DFT workflow.

The role requires a Bachelor's in Electrical/Communications Engineering and 5+ years of deep sub-micron DFT experience, with strong collaboration across RFIC and