Lead DFT Engineer for LEO Satellite ASICs

Amazon Kuiper Manufacturing Enterprises LLC; Ramona (CA); On-site; USD 185,000 - 250,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a Senior DFT Engineer to define and implement DFT solutions for advanced LEO chip SOCs. You will collaborate with ASIC and RFIC teams to ensure robust fault coverage, timing, and power targets while advancing AI-assisted DFT workflows.

The role requires a Bachelor's in Electrical/Communications Engineering and 5+ years in DFT, with experience scripting automation for DFT insertion and validation.

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or related field.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT insertion and validation.

Responsibilities

• Architect and define DFT solutions for various LEO chips.
• Improve IPs and DFT methodology; incorporate AI flow.
• Collaborate with ASIC design teams to integrate DFT logic such as MBIST, clock controls, and JTAG.
• Work with RFIC teams to maximize fault coverage on RF blocks.
• Ensure blocks meet DFT, timing, and power targets with the implementation team.
• Translate ATE patterns to tester format with Test engineering.
• Assist test teams in bringing up digital portions of LEO chips.

Skills

DFT techniques

Automation scripting

AI/ML in HW flow

Cross-team collaboration

Education

Bachelor's degree in Electrical/Communications Engineering

Tools

MBIST

JTAG controllers

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a Senior DFT Engineer to define and implement DFT solutions for advanced LEO chip SOCs. You will collaborate with ASIC and RFIC teams to ensure robust fault coverage, timing, and power targets while advancing AI-assisted DFT workflows.

The role requires a Bachelor's in Electrical/Communications Engineering and 5+ years in DFT, with experience scripting automation for DFT insertion and validation.