Senior DFT Engineer - LEO Chip Design & AI Validation

Amazon Kuiper Manufacturing Enterprises LLC; Coronado (CA); On-site; USD 185,000 - 250,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC in San Diego is seeking a Senior DFT Engineer to define and implement advanced DFT for LEO chips, collaborating with ASIC, RFIC, and test teams to meet timing, power, and fault coverage goals.

This role emphasizes AI/ML-based automation to improve DFT workflows, and requires a strong background in deep sub-micron DFT techniques and experience with MBIST/JTAG.

Qualifications

• Bachelor's degree in Electrical/Communications Engineering, or experience working in electrical engineering field.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation.

Responsibilities

• Architect and define DFT solutions adapted to the specific use of various LEO’s chips.
• Contribute to the improvement and customization of IPs and DFT methodology while embracing AI flow.
• Work with the ASIC design teams in all the sites to incorporate DFT logic like MBIST, clock controls and JTAG controllers.
• Work with RFIC teams to ensure maximum fault coverage on the custom RF blocks.
• Ensure that blocks meet DFT, timing and power targets by working closely with the implementation team.
• Work closely with the Test engineering team to help translate the ATE patterns to tester format.
• Work with the test team to do jointly bring up the digital portions of the LEO chips.

Skills

DFT techniques

Scripting for DFT

Electrical/Communications engineering

Education

Bachelor's degree in Electrical/Communications Engineering

Master's or Ph.D in Electrical/Communications Engineering

Tools

MBIST

JTAG

Job description

Amazon Kuiper Manufacturing Enterprises LLC in San Diego is seeking a Senior DFT Engineer to define and implement advanced DFT for LEO chips, collaborating with ASIC, RFIC, and test teams to meet timing, power, and fault coverage goals.

This role emphasizes AI/ML-based automation to improve DFT workflows, and requires a strong background in deep sub-micron DFT techniques and experience with MBIST/JTAG.