Senior DFT Engineer – AI-Driven ASIC for LEO Chips

Amazon Kuiper Manufacturing Enterprises LLC; Santee (CA); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

RSU eligibility

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a senior DFT engineer to architect DFT solutions for LEO chip SOCs and collaborate with ASIC and RFIC teams across sites. You will drive AI-enabled DFT flows, MBIST, and JTAG integration to ensure robust fault coverage.

The role requires deep sub-micron DFT experience and a strong background in automated script development. Applicants must be US citizens or eligible for export-controlled roles, based in the United States.

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or equivalent experience in electrical engineering.
• 5+ years of experience with advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT insertion and validation.

Responsibilities

• Architect and define DFT solutions for various LEO chips.
• Contribute to IP and DFT methodology improvements while embracing AI-driven flows.
• Collaborate with ASIC design teams across sites to integrate DFT logic (MBIST, clock controls, JTAG).
• Coordinate with RFIC teams to ensure maximal fault coverage on mixed-signal blocks.
• Ensure blocks meet DFT, timing, and power targets with implementation teams.
• Assist Test engineering to translate ATE patterns to tester formats.
• Collaborate with test teams to bring up digital portions of LEO chips.

Skills

DFT techniques

DFT Insertion and Validation scripts

Logic BIST

Automation with AI/ML

RFIC mixed signal familiarity

Education

Bachelor's degree in Electrical/Communications Engineering

Master's or Ph.D in Electrical / Communications Engineering

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a senior DFT engineer to architect DFT solutions for LEO chip SOCs and collaborate with ASIC and RFIC teams across sites. You will drive AI-enabled DFT flows, MBIST, and JTAG integration to ensure robust fault coverage.

The role requires deep sub-micron DFT experience and a strong background in automated script development. Applicants must be US citizens or eligible for export-controlled roles, based in the United States.